FPGA Lock Time and Cascading PLL

[jasonkee111]

Hi

I do have some questions about PLL:

1.  If the same reference clock is connected to 2 PLLs in a device, does the lock time will be the same?  These 2 PLL output clock are in sync?

2.   If the same reference clock is connected to 2 PLLs in 2 FPGA device (same part), does the lock time will be the same?  These 2 PLL output clock are in sync?

3.  Does the output clock of cascading of PLLs are in sync?  Does the signal transfer from PLL1 clock to PLL2 clock need synchronization?

Pls advice

Thanks

[Farabi]

Hello, 

1.  If the same reference clock is connected to 2 PLLs in a device, does the lock time will be the same?  These 2 PLL output clock are in sync?

<ANS> No, you can't control PLL lock time, but you can sync the output clocks to input clock by using PLL compensation mode. 

2.   If the same reference clock is connected to 2 PLLs in 2 FPGA device (same part), does the lock time will be the same?  These 2 PLL output clock are in sync?

<ANS> No, you can't control the PLL lock time. You can sync the output using PLL compensation mode.

3.  Does the output clock of cascading of PLLs are in sync?  Does the signal transfer from PLL1 clock to PLL2 clock need synchronization?

<ANS> They are not synced by default, you need to use PLL compensation mode to sync the clocks. 

regards,
Farabi

[Farabi]

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,

Farabi