FPGA MAX10 in "User-Mode" indication

[Amir21]

Hi,

I'm using DPRs in MAX10-FPGA and init their memory through .hex files.

In order to verify when the FPGA initialization process done,

I'm trying to use the "INIT_DONE" output pin for inidication to release the FPGA external reset signal.

Apparently, I can't find it and enable this pin (INIT_DONE) in Quartus 20.1.1 in the output options.

I'll be glad to know what other possibilities I can use in order to get inidcation for the FPGA enters into "User-Mode" ?

Thanks!

[sstrell]

I think you're looking for CONF_DONE, not INIT_DONE, which you have enabled there.

[Amir21]

Hi,
Since in my design I'm using DPRs which initialized from HEX files, I need to know when the initialization process done.

I'm looking for any valid indication from the FPGA to indicate when it entered into 'USER-MODE' (initialization process finished).

[sstrell]

Well, check this guide to see what you need.  It's either conf_done, nStatus, or maybe through software: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

[NurAiman_M_Intel]

Hi,

SStrell is correct. You can refer to CONF_DONE status to see if the FPGA has enter user mode.

Please refer to the MAX 10 UG as given by sstrell and you can also refer to MAX pin connection guidelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/PCG-01018.pdf

Regards,

Aiman

[Amir21]

Hi,
That's exactly the issue..
The 'CONF_DONE' indication is not enough, I need to know when the initialization process has done..

I tried to find out from the spec how can I use the MAX10 'INIT_DONE' through the Quartus tool, with no success..

[NurAiman_M_Intel]

Hi,

Since INIT_DONE is not mention in the User guide, then there is not INIT_DONE can be check.

The other option is, you can check the status of the I/O pin as per your design. In user mode, the user I/O pins will then function as specified by your design.

Regards,

Aiman

[Amir21]

Hi,
Sounds like a good idea, I will definitely try it.

In addition,
Any idea until when the FPGA reset should remain valid, when we use the DPR IP in my design?

Best Regards,
Aizik Amos.

[NurAiman_M_Intel]

Hi,

Sorry but what is DPR IP?

Regards,

Aiman

[Amir21]

Hi,
I actually meant to the IP Component -
RAM: 2-Port

Best Regards,
Aizik Amos.

[NurAiman_M_Intel]

Hi,

Please refer to Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide for information on RAM. Or you can open a new case for embedded memory questions.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf

Regards,

Aiman

[NurAiman_M_Intel]

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