FPGA PLL minimum frequency

[tommino]

Hello,

My baseline design is to use a PLL to multiply (by a factor 1000 or so) an incoming clock signal of about 1 kHz. Is there any FPGA family with such a low frequency input for the PLL? 

If the above mentioned operation is not feasible, I think I will have to generate inside the FPGA (not selected yet so feel free to reccommend one) two clock signals : the first shall have a frequency of about 1 kHz and the second of about 1 MHz. 

Could you please help me in assessing which is the best (in terms of feasibility annd jitter performance)  solution?  

[Ash_R_Intel]

Hi,

There are no devices with such low frequency input for PLL.

It is easier to get a high frequency clock and divide it to generate lower frequency.

Regards