Hello all,FPGA power measurement is very important to estimate the efficiency of the applied algorithm using OpenCL (or an HDL), nevertheless i couldn't find a way to measure the power needed by the FPGA in the DE10-Nano board, especially at run time. is there some way at least to estimate the power consumption of a compiled OpenCL Kernel, is it feasible to use the amp-meter on the FPGA board? Thanks in advance
If it isn't too late, I'm currently working on a way to power estimate the consumption of a OpenCL kernel running in the DE10-Nano FPGA.
And I'm basing my attempt on this paper: http://lad.dsc.ufcg.edu.br/lad/uploads/Lad/WCAS_2017_8.pdf