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FPGA Programming Via USB instead of Programming Pod

joe306
New Contributor I
437 Views

Hello, I see that Digilent has a JTAG-SMT-NC module that allows the Xilinx tools to program the FPGA over USB with any FPGA programming pod. Does anyone know if there is such a chip that supports the Quartus tools?

 

https://digilent.com/shop/jtag-smt4-surface-mount-programming-module/

 

Thank you

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1 Solution
SimonRichter
New Contributor I
401 Views

Hi,

you can use any JTAG adapter you want, or build your own, provided you don't use SignalTap or time-limited components -- these two features still require the Altera USB Blaster.

For any other design, convert your file to SVF format, that lists the exact sequence of JTAG signals to initialize the FPGA in a readable format that can be interpreted e.g. by OpenOCD.

    Simon

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6 Replies
NurAiman_M_Intel
Employee
418 Views
joe306
New Contributor I
409 Views

Hello and thank you for responding to my post. No, I'm talking about a chip that will allow you to connect to your FPGA's JTAG via USB and the Quartus tools will be able to program the boot code onto the FPGA or the FPGA's boot memory. So you don't need a USB Blaster programming pod. Take a look at Digilents chips: 

 

https://digilent.com/shop/jtag-smt2-surface-mount-programming-module/

 

All I do is use this module connect it up as the datasheet instructs and the Xilinx tools will be able to interface with it and program your FPGA. 

I was wondering if there was such a chip that supports the Intel FPGA's and tools. 

Very cool, don't need a USB blaster only a USB cable. 

Respectfully,

Joe

NurAiman_M_Intel
Employee
403 Views

Hi,


Sorry to tell you that we do not have that chip. We do not have USB Blaster chip embedded on board.


Regards,

Aiman


SimonRichter
New Contributor I
402 Views

Hi,

you can use any JTAG adapter you want, or build your own, provided you don't use SignalTap or time-limited components -- these two features still require the Altera USB Blaster.

For any other design, convert your file to SVF format, that lists the exact sequence of JTAG signals to initialize the FPGA in a readable format that can be interpreted e.g. by OpenOCD.

    Simon

joe306
New Contributor I
392 Views
NurAiman_M_Intel
Employee
340 Views

 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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