Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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FPGA Transceiver connection

Altera_Forum
Honored Contributor II
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I have designed Cyclone V based board. 

 

I have connected SFP TX and RX pin in transceiver, as attached. 

 

In this I need to clarify, whether REFCLKL[0,1]P, N should be connected to differential clock or no need. 

 

How it will affect SFP data transfer. Please support.
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Altera_Forum
Honored Contributor II
133 Views

Refer to the Input Reference Clocking chapter in device handbook. Dedicated refclk pin is the preferred clocking option, usually single ended clock is sufficient.

Altera_Forum
Honored Contributor II
133 Views

 

--- Quote Start ---  

I have designed Cyclone V based board. 

 

I have connected SFP TX and RX pin in transceiver, as attached. 

 

In this I need to clarify, whether REFCLKL[0,1]P, N should be connected to differential clock or no need. 

 

How it will affect SFP data transfer. Please support. 

--- Quote End ---  

 

 

Hi Karthik, 

 

For your information, if you are using the transceivers channels in the device, the refclk should be of differential. You may refer to the CV device datasheet -> "Table 20: Reference Clock Specifications for GX, GT, SX, and ST Devices" and you should see only differential IO standards are supported. 

 

Best Regards, 

bfkstimchan 

(This message was posted on behalf of Intel Corporation)
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