FPGA early input output planning

[Altera_Forum]

Hello friend , 

 I am working on Cyclon 3 FPGA, EP4C487.I use this FPGA to implement Glue logic.Right now i am not implemeting my software to FPGA, but only designing my PCB. To design schematic of pcb i need to coneect 19 address line and 15 data line (from BF537 DSP) to FPGA.But as it is myfirst project.I little bit confuse how can i assigen FPGA pin to this data and address pin.So please guide me or give me some link from where i can get some idea.

[Altera_Forum]

Hi Sameerr11, 

 First of all, the partnummer you mention is unknown. Probably a typo. Making an early pin planning is not to difficult. I suppose you have Quartus II installed. Lets take a schematic as a toplevel.  - Open QII. - select file > new > Quartus II project - In the wizard, answer all the questions. - When finished, select file > new > block diagram/schematic file  - Select the symbol tool at the left of the schematic (AND symbol) - Unfold till you get pin: bidir, input, output - Put the appropiate pins in the schematic - Change names (address-bus could be A[18..0]) - Save under the same name as project name - Start Analysis & Sythesis - Ignore warnings about "missing source" - When finished, go to assignments > pins - Assign the pins. - Redo Analysis & Sythesis  Finished. Just to give you a quick start. I probably forgot some steps. Check the QII handbook for details.  Good luck, Ton

[Altera_Forum]

part no is EP3C40F484C7 (sorry for my mistake)

[Altera_Forum]

Hello,  

 I also recommend that you double check every pin against the Cyclone III pin connection guidelines. And triple check every power pin. :D  http://www.altera.com/literature/dp/cyclone3/pcg-01003.pdf

[Altera_Forum]

thank you for above process..I did same as u said but i have problem after below step... 

 When finished, go to assignments > pins  Assign pin,How can i assigne pins for add[19...1].I want to use bank 3 and 4 ... there are pin like DIFF_n,DIFF_p,DQ, Other dual purose(this is all symbole name from pin legend)..I dont know , how can i assigen pin to it ?

[Altera_Forum]

Hi,  

 There's one more important step I forgot to mention: Assignments -> Device -> Device and Pin Options You need to double check the settings on those tabs. Some will be fine by default, some you won't care, some you'll need to change. But you must be very sure about each is each. This will take you a bit of digging through the literature.  Back to pin assignment, when you hover the mouse over a pin, it lists the pin's multiple functions/capabilities. What you need are pins which include the "I/O" function -- by far, the most common type of pin. The pin's caption will, probably, list other functions/features but do not worry about them.  After that, synthesize your design. It's very possible that, at the first attempt, synthesis will fail because you have invalid pin assignments.  If that happens, you need to research the error, fix the assignment and synthetize again.  There are so many rules for FPGA pin assignment that it's nearly impossibe to get it right at first attempt. That's why it is so important to create a top level module, assign the pins and the synthetize the design, so that tools can report errors.

[Altera_Forum]

--- Quote Start ---  thank you for above process..I did same as u said but i have problem after below step...  When finished, go to assignments > pins  Assign pin,How can i assigne pins for add[19...1].I want to use bank 3 and 4 ... there are pin like DIFF_n,DIFF_p,DQ, Other dual purose(this is all symbole name from pin legend)..I dont know , how can i assigen pin to it ?  --- Quote End ---    Yes you can assign your signals to pins labeled DIFF_n and DIFF_p. These can be used in pairs for differential signals, but when you use single ended signals, like your address and data bus, they can be used individually. Just try. If you make a mistake, Quartus will complain.  Good luck, Ton

[Altera_Forum]

The column pin name/function is the primary pin description. All pins designated as IO can be used as single ended input or output without restriction. 

 optional Functions are - optional.