FPGA logic lock and increase frequency

[GDeXi]

In my design, there are two parts running at different frequencies, and one of them has been debugged stably without any problems. Now I want to lock down the part without problems to reduce compilation time and increase frequency as much as possible.I haven't done this kind of work before. All I want to ask is what I need to do in the software, and whether there are corresponding tutorials and documents for reference. It's better to use the series of aria 10 and stratix10

[sstrell · Accepted solution]

Set the part of your design that is done as a design partition: right-click it in the design hierarchy in the project navigator and set it as a design partition. You can create a Logic Lock region for it as well, but once you set it as a design partition, you can choose to reuse the post-fit netlist to prevent it from changing. See the block-based design user guide for info on incremental block-based compilation and the linked online training:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-qpp-block-based-design.pdf

https://www.intel.com/content/www/us/en/programmable/support/training/course/oibbc100.html

#iwork4intel

[Kenny_Tan]

Firstly, any reason u want to increase the frequencies on one particular design partition?

Are you using singal tap for debugging? Does your timing closed before you signal tap?

[Kenny_Tan]

Any update?