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Altera_Forum
Honored Contributor I
991 Views

FPGA to HPS (AXI Slave) address range issue

Hi People, 

The Background : Part Cyclone V, Tools Q17, QSys 

Task: To connect a MM Master Peripheral to write to Slave AXI of HPS  

 

I'm using QSys (staring from a DE10_NANO_SoC_GHRD example) and want to be able to write from an external IP to the SDRAM via HPS. 

 

The f2h_axi_slave interface has a range 0x0000_0000 to 0xFFFF_FFFF (and apparently I can't change it the range not sure why) 

The master is an "External Bus to Avalon Bridge" with address range of 1MB (0x0000_0000 to 0x000F_FFFF)  

 

when I try to connect the master avalon with the Slave AXI (I hope this is legal in Qsys) I get an error which sounds rather funny 

 

error: soc_system.bridge_0.avalon_master: hps_0.f2h_axi_slave (0x0..0xffffffff) is outside the master's address range (0x0..0xfffff) 

 

let's not blame the tools yet, hence the question: I'm doing something fundamentally wrong here? 

 

Thanks, 

Aurash 

 

PS - data width of both HPS AXI Slave and "External Bus to Avalon Bridge" is matched (128 bits) 

 

 

PS2 - I just tried to connect the "External Bus to Avalon Bridge" (Master) to f2h_sdram0_data (Avalon Memory Slave) but I'm getting the exact same error - my guess is that the address bus width has to be matched between the two. (not sure how)
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Altera_Forum
Honored Contributor I
137 Views

I hate to answer to myself... 

 

It seems that the hps_0.f2h_axi_slave is expecting 32 bit of address but the external bus to avalon bridge is exposing the address bits to cover the range specified in the UI hence the mismatch. 

I edited the tcl file of the peripheral and the verilog source code and is working now. 

If someone from Altera is reading the forum I would suggest to change the error message from (0x0..0xffffffff) is outside the master's address range (0x0..0xfffff)  

into something more specific. (like address width mismatch between the master and the slave) 

Thanks in advance, 

A
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