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FPGA2HPS Bridge Bandwidth Issue

Altera_Forum
Honored Contributor II
‎05-21-2014 09:35 PM
1,441 Views

Hi, 

 

I am trying to use the FPGA2HPS bridge to grab onscreen display frames from the ARM's memory. The FPGA2HPS bridge is set up as 128 bit bus. 

 

I have two VIP Frame Readers: 

VFR#1: 1920x1080 (RGBA) with 128 deep FIFO and 64 burst count 

VFR#2: 1024x768 (RGBA) with 32 deep FIFO and 16 burst count 

 

The bridge and the VFR avalon busses are clocked at 148.5MHz. 

 

I am getting underflow at the CVO when trying to get frames from the VFR# 1. No issue in getting frames from VFR# 2. 

 

Is the FPGA2HPS bridge bandwidth limited? I was thinking of using the FPGA2SDRAM interface but it seems rather complicated to set up. 

 

Any suggestion on how I can resolve my issue? 

 

Thanks!
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Altera_Forum
Honored Contributor II
‎05-21-2014 09:36 PM
710 Views

Forgot to mention - I'm using Cyclone V SX SoC development board with 1GB memory on the ARM side.

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Altera_Forum
Honored Contributor II
‎05-28-2014 03:47 PM
710 Views

Anyone on the forum able to provide some guidance???

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Altera_Forum
Honored Contributor II
‎06-04-2014 10:51 AM
710 Views

I'd like to know the solution as well.

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