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hi,
I have a Moprh-IC-II board and I'm trying to communicate via USB with a FT2232H in Sync FIFO Mode and D2XX Drivers. I manage to have the 60MHz clock input (my main fpga clock) from the ft2232h, and i can transfer data from the PC to my fpga via ft2232h with FT_Write(). FIFO Mode seems to work as expected on this side. The RXF# signal is working, going low when needed (I'm checking signals with SignalTap). But I can't send data from my fpga to the pc, the TXE# signal (active low) is stuck high and I can't find how to have it low to be able to receive data... If you have any idea on what my issue could come from ? Tank you, AlexisLink Copied
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I can't say for sure, I've used the FT2232 many times and not had this problem. Have you checked the obvious, TXE# is connected to an FPGA input pin and not an output being driven high? Have you tried clearing the transmit buffer with FT_Clear()? Have you actually issued an FT_Read()? Does the FT_Read() come back with an error, timeout, etc? What is your host system/OS?
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Hi,
--- Quote Start --- Have you checked the obvious, TXE# is connected to an FPGA input pin and not an output being driven high? --- Quote End --- Already checked, I proceeded the same way (with a different name of pin obviously, according to the datasheet) with TXE# and RXF# and RXF# works perfectly. --- Quote Start --- Have you tried clearing the transmit buffer with FT_Clear()? --- Quote End --- If by FT_Clear you mean FT_Purge without success, I've tried this (can't find any FT_Clear in the D2XX Programmer's guide). --- Quote Start --- Have you actually issued an FT_Read()? Does the FT_Read() come back with an error, timeout, etc? What is your host system/OS? --- Quote End --- I can call FT_Read() without any error but I will always have 0 BytesReceived (even if I ask to read several bytes), which is kind of normal because FT_GetQueueStatus always says there is nothing in the receiving buffer. TXE# high telling me the ft2232h is never ready to receive any data. I'm on Windows7 (32-bit). I load my fpga by USB through the channel B of my fifo with the MorphLd Utility, could this be somehow related? Edit : loading fpga by JTAG doesn't change anything. Many thanks for your help, I'm kind of new to this whole thing. Alexis- Mark as New
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Hi,
--- Quote Start --- Check here http://electro-logic.blogspot.it/2014/03/fpga-comunicazione-ad-alta-velocita_99.html?m=1 --- Quote End --- I've already checked this useful blog, but I can't find what I did differently in my Software part, which I suppose being where my problem come from (receiving buffer not ready to receive). I'm using D2XX drivers and not libftdi this shouldn't make a huge difference... Here are my actions when trying to configure my device : - FT_OpenEx - FT_ResetDevice - FT_Purge - FT_SetBitMode - Reset Mode - FT_SetBitMode - Sync FIFO Mode - FT_SetLatency - 2ms - FT_SetUSBParameters (64 Bytes each) - FT_setTimeOuts Alexis- Mark as New
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Do you realize that in Sync FIFO mode the FT2232 is a single channel device? When you load your fpga through channel B it must somehow reconfigure the FT2232 for dual channel mode. Are you sure you're switching back to single channel when you try to run in sync FIFO mode?
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Hi,
--- Quote Start --- Do you realize that in Sync FIFO mode the FT2232 is a single channel device? When you load your fpga through channel B it must somehow reconfigure the FT2232 for dual channel mode. Are you sure you're switching back to single channel when you try to run in sync FIFO mode? --- Quote End --- I'm not sure to fully understand what you mean, I'm sure to use channel B to load my FPGA (with MorphLd utility) and then I use a little GUI made with CVI-LabWindows where I only connect to channel A. I manage to have the clock at 60mhz from the fifo in my fpga and the rxf# working fine make me think it's not a problem of channels. Alexis- Mark as New
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Yes, you're probably right if you're getting a 60Mhz clock.
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Hi,
The EEPROM seems right, the Software part too, and I have tested on an other Morph-IC-II to be sure there is no short circuit or bad solder. I'm a bit lost again, I don't where to look or what to try anymore. Thank you again for your help and ideas. Alexis- Mark as New
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Here's some of the code I used to configure channel A for sync fifo mode. Maybe something will stand out.
UCHAR Mask_A = 0xff; // all outputs UCHAR Mode_A = 0x40; // high speed synchronous fifo UCHAR Reset_Mode = 0x00; UCHAR LatencyTimer = 2; // connect with Channel A and set Mode ftStatus = FT_Open(device_number_a, &FTDIHandle_A); FT_SetBitMode(FTDIHandle_A, 0xff,Reset_Mode); Delay(.01); FT_SetBitMode(FTDIHandle_A, Mask_A,Mode_A); FT_SetLatencyTimer(FTDIHandle_A, LatencyTimer); FT_SetUSBParameters(FTDIHandle_A,65536,65536); FT_SetFlowControl(FTDIHandle_A,FT_FLOW_RTS_CTS,0x00,0x00); FT_SetTimeouts(FTDIHandle_A, 5000, 5000);- Mark as New
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I'm using approximately the same, just trying with smaller buffers (64 bytes) to have something working first.
Do you know when your TXE# goes low, after which step ? Because mine is low at the beginning, goes high when the mode is set to sync fifo, and then never goes low, no matter what I'm doing. Alexis.- Mark as New
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I've not worked with the hardware in some time, so I couldn't say exactly when TXE# goes low.
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Hi,
--- Quote Start --- Here's some of the code I used to configure channel A for sync fifo mode. Maybe something will stand out. UCHAR Mask_A = 0xff; // all outputs UCHAR Mode_A = 0x40; // high speed synchronous fifo UCHAR Reset_Mode = 0x00; UCHAR LatencyTimer = 2; // connect with Channel A and set Mode ftStatus = FT_Open(device_number_a, &FTDIHandle_A); FT_SetBitMode(FTDIHandle_A, 0xff,Reset_Mode); Delay(.01); FT_SetBitMode(FTDIHandle_A, Mask_A,Mode_A); FT_SetLatencyTimer(FTDIHandle_A, LatencyTimer); FT_SetUSBParameters(FTDIHandle_A,65536,65536); FT_SetFlowControl(FTDIHandle_A,FT_FLOW_RTS_CTS,0x00,0x00); FT_SetTimeouts(FTDIHandle_A, 5000, 5000); --- Quote End --- TXE# should obviously be low after this kind of settings or am I missing / misunderstanding something ? Alexis.- Mark as New
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Hi,
SOLVED : I'm not using the "USB Remote WakeUp" mode, and the master I had taken from the FTDI project of AN_165 was completely ignoring the pin SIWU. At first sight, it seemed quite ok and I didn't question it. BUT, when unused, the SIWU pin has to receive '1'... PS: is it possible to mark a thread as Solved in alteraforum? I'd like to THANK YOU gj_leeson for everything you've done to help me! Alexis.- Mark as New
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I'm glad you solved your problem. I didn't even think about the SIWU pin as I've always tied it HI.
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Hi,
Do you know the datarate you've reached with this setup ? I've reached 32MBytes/s this far, but the size of buffers or the data latency timer don't seem to change anything on my datarate. Alexis.- Mark as New
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For big transfer buffer size and data latency doesn't affect speed.
For small transfer I set latency to 1 ms and use SIWO. Key to improve performance is to make less bigger Write call to use less USB microframe. I reached 50 MB/S in read and 14 MB/S in read (see last image into http://electro-logic.blogspot.it/2014/02/fpga-comunicazione-ad-alta-velocita_16.html)- Mark as New
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Thank you for your feedback.
Is it normal not to receive those "2 status bytes" that I've read about in many datasheets about usb transfer ? Alexis;- Subscribe to RSS Feed
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