Failure Analysis on MAX10 FPGA

[Pat2]

We have a customer field return, and the failure was isolated to to a bad clock output from pin N4 onthe MAX10 (196 UBGA).  This is a singular failure, not a widespread issue, but it is a field return on a unit that previously passed all tests.  We suspect the MAX10 was damaged somehow, or may have a latent defect.  Can we get failure analysis on this device, please?

I work for Infinera, and our board CM is Jabil.

Thanks,

Pat

[Zawani_M_Intel]

Dear Pat2,

Thank you for using Intel FPGA Community Forum.

We have sent you a private email to continue support your FA request.

Thank you. Have a great day!

Wani