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We received an encrypted IP core from "Praesum Communications" to use on our Arria 10 GX FPGAs. Platform Designer is able to generate HDL and the IP Generation compilation step work, however, when it gets to Analysis and Synthesis, I get a lot of “decryption of data_block failed” errors. The IP core was encrypted using Quartus 22.2 on Linux. I am compiling on Windows 10 and have tried both Quartus 20.2 and 22.2, but receive the same errors in both cases. I found this help article (link below) referencing line ending issues, so I converted all line endings to Windows using unix2dos, but that did not resolve the issues.
https://www.intel.com/content/www/us/en/support/programmable/articles/000080956.html
Any recommendations?
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Have you consult the vendor IP beforehand? Since they are the one providing the IP so they should know if one or more of their end customer having similar issue. Also, can check whether the IP is encrypted using Quartus or third party tool?
Is the IP able to compile without encryption in first place?
Could you provide me the IP so I can investigate?
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Hi,
The IP compiles and regenerates fine in Platform Designer.
The IP vendor is pursuing it with Intel. They said that it was encrypted using Quartus.
I think the client is working with Intel directly.
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If the IP is encrypted in Quartus using IEEE, by right it should be able to compile.
Is the vendor IP currently working with the Intel on resolving the issue?
Do you still need my help? If so, I need a way to duplicate the issue from my end. e.g. a dummy IP.
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Do you need help in regards to this case?
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Since there are no feedback for this thread, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.
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