Such message I always get each time I tried to generate a Qsys project in my computer:
Info: Interconnect is inserted between master pb_dma_to_descriptor_ram.m0 and slave descriptor_memory.s1 because the master has address signal 14 bit wide, but the slave is 11 bit wide.
Info: Interconnect is inserted between master pb_dma_to_descriptor_ram.m0 and slave descriptor_memory.s1 because the master has read signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master pb_dma_to_descriptor_ram.m0 and slave descriptor_memory.s1 because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
Info: avalon_st_adapter: Inserting timing_adapter: timing_adapter_0
Info: addr_io_in: Starting RTL generation for module 'q_sys_addr_io_in'
Info: addr_io_in: Generation command is [exec C:/altera/18.1lt/quartus/bin64/perl/bin/perl.exe -I C:/altera/18.1lt/quartus/bin64/perl/lib -I C:/altera/18.1lt/quartus/sopc_builder/bin/europa -I C:/altera/18.1lt/quartus/sopc_builder/bin/perl_lib -I C:/altera/18.1lt/quartus/sopc_builder/bin -I C:/altera/18.1lt/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/18.1lt/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/18.1lt/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=q_sys_addr_io_in --dir=C:/Users/MyDome/AppData/Local/Temp/alt8925_6419140557429175281.dir/0005_addr_io_in_gen/ --quartus_dir=C:/altera/18.1lt/quartus --verilog --config=C:/Users/MyDome/AppData/Local/Temp/alt8925_6419140557429175281.dir/0005_addr_io_in_gen//q_sys_addr_io_in_component_configuration.pl --do_build_sim=0 ]
Info: addr_io_in: perl: warning: Setting locale failed.
Info: addr_io_in: perl: warning: Please check that your locale settings:
Info: addr_io_in: LC_ALL = (unset),
Info: addr_io_in: LANG = (unset)
Info: addr_io_in: are supported and installed on your system.
Info: addr_io_in: perl: warning: Falling back to the standard locale ("C").
Error: addr_io_in: Failed to generate module q_sys_addr_io_in
Info: addr_io_in: Done RTL generation for module 'q_sys_addr_io_in'
Info: addr_io_in: "q_sys" instantiated altera_avalon_pio "addr_io_in"
Error: Generation stopped, 42 or more modules remaining
Info: q_sys: Done "q_sys" with 34 modules, 2 files
Error: qsys-generate failed with exit code 1: 2 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis
Device name DESKTOP
Processor Intel(R) Core(TM) i7-10750H CPU @ 2.60GHz 2.59 GHz
Installed RAM 32.0 GB (31.8 GB usable)
Device ID XXX
Product ID XXX-AAOEM
System type 64-bit operating system, x64-based processor
Pen and touch Pen and touch support with 10 touch points
Edition Windows 10 Pro
Installed on 22/?10/?2020
OS build 19043.1288
Experience Windows Feature Experience Pack 120.2212.3920.0
Development environment info
any, current version is 18.1.
This is only in this computer environment, under any project and with any version of development environment (I tried from 14.0 till 20.0).
What is this? how to fix that?
See also screen shot.
What is the system component that is failing? There is no info here about it. Is this an IP? How is it parameterized and connected to the rest of your system? The screenshot doesn't show this. More info needed on the component that is actually causing the failure.
Please pay attention that this is the FATAL error: QSYS builder cannot work at all with any project.
Any QSYS IP that is the first in the instantiation queue is failed and followed by the message about all further IPs
in the queue also to be failed.
In the simple test case project with only JTAG UART and On-Chip SRAM, QSYS fails on the first of these two in the queue
(JTAG UART, for instance).
So, no any specific component (QSYS IP) that causes this failure.
And no any specific QSYS project that causes this failure.
And no any specific Quartus/QSYS version(s) that causes this failure.
In my opinion, something wrong with Perl Run-Time Machine that is specific for only this computer environment.
Could you try to install the latest Quartus version (21.1 for lite/standard, 21.3 for pro) and check whether the issue persists.
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.