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Valued Contributor III
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Fifo Controller with external memory help needed

Hi All, 

I'm new to FPGAs and CPLDs, and I have checked the forum for similar discussions already, so please forgive any repetition here if there is any. 

 

I'm using a MAX II EPM2210F324C3 to design a FIFO controller. I'm planning to use external memory to store data and heading more towards SDRAM over SRAM. 

 

I need to store data 8 bits wide by 251904 bytes deep at least twice. (so double the depth). 

 

I'm trying to use the megawizard to develop a FIFO controller and I can't make a controller deeper than 2048 words. 

 

The question is, how do I make the FIFO deep enough with the functionallity given in the mega wizard? 

 

Regards, 

Adam
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