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ZSism
Beginner
129 Views

For Cyclone 10 LP can I use +1.8V or +3.3V VCCIO in a BANK where I connect an LVDS input?

Hi,

 

I am using Cyclone 10 LP 80k. I have an LVDS clock connected to the dedicated clock inputs of the FPGA. In the datasheet and connection guidelines I couldn't find which rail powers the differential input buffers.

 

I understand that for an LVDS output the BANK requires +2.5V VCCIO so that it can create appropriate common mode voltages. However I think for an LVDS input I am not sure if such a requirement exists since biasing etc is external and if input has a truly differential buffer then it should not need specific VCCIO just for receiving this signal.

 

I have two questions:

  • Are LVDS input buffers of Cyclone 10LP powered by VCCINT as in the older Cyclones? Can I use 1.8V, 3.3V VCCIO in a BANK where I am also connecting an incoming LVDS signal?
  • I am using an LVDS clock to drive DIFFCLK_P, _N pins of a BANK. Does that BANK have to have +2.5V VCCIO?

 

Kind regards,

Zeki

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1 Reply
ShafiqY_Intel
Employee
61 Views

Hi Zeki,

 

The LVDS of Cyclone 10 LP is only powered by 2.5V. It do not support VCCINT as in the older Cyclones.

In addition, only the I/O banks 1, 2, 4, and 6 support the LVDS(dedicated) I/O standard. 

 

Please refer below for more details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...

 

Regards,

Matt