Hi,
I am using Cyclone 10 LP 80k. I have an LVDS clock connected to the dedicated clock inputs of the FPGA. In the datasheet and connection guidelines I couldn't find which rail powers the differential input buffers.
I understand that for an LVDS output the BANK requires +2.5V VCCIO so that it can create appropriate common mode voltages. However I think for an LVDS input I am not sure if such a requirement exists since biasing etc is external and if input has a truly differential buffer then it should not need specific VCCIO just for receiving this signal.
I have two questions:
- Are LVDS input buffers of Cyclone 10LP powered by VCCINT as in the older Cyclones? Can I use 1.8V, 3.3V VCCIO in a BANK where I am also connecting an incoming LVDS signal?
- I am using an LVDS clock to drive DIFFCLK_P, _N pins of a BANK. Does that BANK have to have +2.5V VCCIO?
Kind regards,
Zeki
