I am using Cyclone 10 LP 80k. I have an LVDS clock connected to the dedicated clock inputs of the FPGA. In the datasheet and connection guidelines I couldn't find which rail powers the differential input buffers.
I understand that for an LVDS output the BANK requires +2.5V VCCIO so that it can create appropriate common mode voltages. However I think for an LVDS input I am not sure if such a requirement exists since biasing etc is external and if input has a truly differential buffer then it should not need specific VCCIO just for receiving this signal.
I have two questions:
The LVDS of Cyclone 10 LP is only powered by 2.5V. It do not support VCCINT as in the older Cyclones.
In addition, only the I/O banks 1, 2, 4, and 6 support the LVDS(dedicated) I/O standard.
Please refer below for more details: