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For Max 10 , the POR circuitry monitors VCCIO , but there is a condition .
For banks 1B and 8 for all Intel MAX 10 devices and banks 1 and 8 for the 10M02 device. So if the JTAG is not fall in to these banks it is okay to connect as per my understanding.
Reference page no: 8
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf
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