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For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

The VCCIO is 3.3V. Thank you!

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Re: For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Hi,

 

Why can't we use IO_STANDARD to "3.3-V LVTTL" ???

which device are you using?

 

  1. Yes, you can use it(check respective device datasheet). but you have Apply series termination or enables the PCI-clamp diode(by default its ON). refer an447 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an447.pdf
  2. Diode clamped voltage can still exceed the maximum DC and AC specifications due to the high VCCIO voltage level of the bank in which the I/O resides. You must manage the voltage overshoot. You can leave the diode enabled without concern for the DC current as the I/O pin is not overdriven.

 

Regards

Anand

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Re: For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Hi Anand!

 

I am using MAX10 device.

 

These FPGA pins are used to interface with a data bus, which is shared between multiple ICs on the PCB; because of that there are some extra stray capacitance present, so extra current capabilities might be desirable.

I think using 3.0-V-LVTTL I/O standard has more Current Strength capabilities (4 mA, 8 mA, 12 mA, 16 mA, Max) vs. 3.3-V-LVTTL (4 mA, 8 mA, Max). Do you agree?

Do you know to what value Max corresponds to?

 

When we talked about PCI-clamp diode. What is PCI stands for?

 

Thank you,

Andrey

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Re: For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Hi Andrey,

 

You can use 3.0-V LVTTL" I/O standard with VCCIO 3.3V.

But to have a signal of 3.3v it should match the vih and vil requirements with respect to 3.0-V LVTTL" I/O standard.

 

I think using 3.0-V-LVTTL I/O standard has more Current Strength capabilities (4 mA, 8 mA, 12 mA, 16 mA, Max) vs. 3.3-V-LVTTL (4 mA, 8 mA, Max). Do you agree?

Yes,you are correct refer table 4 from below link.

 

Do you know to what value Max corresponds to?

Max current is depended on the driver/ receiver and FPGA. It will be around maximum absolute value.To get exact max current we need to do IBIS simulation by having both IBIS model.

Intel recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.

 

When we talked about PCI-clamp diode. What is PCI stands for?

PCI (Peripheral Component Interconnect)-bus clamp diodes in the FPGA’s I/O blocks to prevent damage to the FPGA (Figure 1). The PCI clamp diode limits the voltage to a level that doesn’t harm the input.

 

Refer link for more information

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an447.pdf

 

Regards

Anand

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Beginner
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Re: For the input FPGA pin, can I configure the IO_STANDARD to "3.0-V LVTTL" if the signal comes at 3.3V level? Is it safe for FPGA I/O operation? Are any pros and cons of using "3.0-V LVTTL" I/O standard when signal is at 3.3V level?

Thank you for your help, Anand!

Best regards,

Andrey

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