Fractional PLL Drifting Cyclone V

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Device: 5CSXFC5C6U23C7N 

Silicon Revision: B Software: Quartus II 13.1 update 3 OS: Windows 7  I have been seeing the Fractional PLL drift with respect to the reference clock when either the Dynamic Reconfiguration port is enabled or if the downstream cascading port (adjpllin) is enabled. When either of these options are enabled it brings the "DSM Order" option into view.   I have simplified a project to include the bare minimum and have recreated the problem.   If I leave the PLL in Fractional mode with the Dynamic Reconfiguration off and disable the "adjpllin" port, the PLL output does not drift. If I enable the Dynamic Reconfiguration port, the PLL output will drift roughly 1ns per minute.   The drift is smoother with a 3rd order DSM set. If the DSM order is set to 1st order, the PLL output drift jumps every once in a while.   While the PLL output is drifting, the LOCK output stays high (as if it was always locked and never lost lock). I have attached a picture of my simplified design that shows my PLL output drifting with respect to the reference clock.  Has anyone seen anything similar or have any suggestions? I have also attached the simplified project as a .zip so all the files are contained.  Thank you,  Rob  https://www.alteraforum.com/forum/attachment.php?attachmentid=8638