Frequent loss of transceiver CDR lock

[SJadh1]

Hello,

I am using Arria10 GX development kit.

I am working on USB protocol. I have configured transceiver in pcs direct mode. I am seeing that transceiver lose CDR lock(lockedtodata) signal frequently during high speed data transfer. In what scenarios CDR may lose lock during high speed data transfer.

To rule out problem with channel I have executed transceiver toolkit so as to optimize PMA setting.

Thanks & Regards,

Sachin Jadhav

[CheePin_C_Intel]

Hi Sachin,

As I understand it, you have some inquiries related to the CDR lose lock-to-data. For your information, the following are general cause of CDR lose lock causes for your reference and to further debug into:

1. No valid signal present or there is an issue with signal integrity which violate the RX input specs. You may try to probe the eye diagram using oscilloscope to check on the Eye diagram quality. Then perform PMA tuning to see if it helps. You may also try to enable internal serial loopback to see if CDR can lock?

2. The ppm difference between the CDR refclk and incoming data clock domain exceed the configured ppm frequency threshold setting.

3. The CDR output clock and the input reference clock are not phase matched within approximately 0.08 unit interval (UI) (phase locked).

4. You may also want to ensure the CDR refclk and the mgmt_clk are directly sourced from free-running oscillators on board and with correct frequencies to isolate any power up calibration related issues.

Please let me know if there is any concern. Thank you.

Chee Pin

[SJadh1]

Hi Chee Pin,

Thank you for reply.

I have obtained optimal PMA setting for clean reception using transceiver toolkit. I can see CDR getting locked with internal serial loopback and external serial loopback and tested with transceiver toolkit.

Can you elaborate more on Point#3 mentioned by you. How can I verify it.

Does Altera transceiver supports CDR ppm configuration of more than 1000 ppm ?

Thanks & Regards,

Sachin Jadhav

[CheePin_C_Intel]

Hi ,

Regarding the point#3, you would need to use oscilloscope to probe both the recovered clock from the CDR ie rx_pma_clkout and the input refclk to CDR to check for phase difference.

As for the CDR ppm tolerance, the max is =/-1000ppm only. You may refer to the device datasheet -> "CDR PPM tolerance" section for further details.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin