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GPIO state of ARRIA 10 FPGA during Power up & during configuration

HBhat2
New Contributor II
149 Views

Hi,

I want to know whether the GPIOs in the arria 10 GPIO bank remain in High impedance/Tri-state  during power up sequencing.

Where I can get the information regarding this. Which document clear mentions this point. I gone through Arria 10  handbook & pin connection guidelines. Nowhere the IO state of Arria 10 FPGA during power up is mentioned. Please provide the appropriate reference to know what will be the state of IOs during FPGA power up (& during configuration).

With regards,

HPB

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3 Replies
AminT_Intel
Employee
137 Views

Hello,

 

The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The configuration
cycle consists of 3 stages—reset, configuration, and initialization. While nCONFIG is low, the device is in
reset. When the device comes out of reset, nCONFIG must be at a logic high level in order for the device
to release the open-drain nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA is ready to receive configuration data. Before and during configuration, all user I/O pins are tristated. Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins
which are on, before and during configuration.

 

You can refer to this document for more information: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cfg/cfg_cf51001.pdf

 

Thank you.

HBhat2
New Contributor II
132 Views

Hi,

Thank you for the response.  

1) Before and during configuration, all user I/O pins are tristated.

2) Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins
which are on, before and during configuration

I just confused with these 2 points. Point 1) says IO pins are tristated. & point 2 says IOs have weak pull-ups. 

My confusion is if weak pull up is connected to IOs before & during configuration, what is the meaning of tristated (point 1)?

Whether this means that the internal IO buffers of FPGA is not connected to the pins (tristated) but FPGA IO pins are pulled up with resistors so that when we physically measure the voltage before or during configuration, we can get VCCIO voltage level?

With regards,

HPB

AminT_Intel
Employee
124 Views
Hello,
 

Tri-state means a state of high impedance. Like example, a pin can be pulled to certain voltage or become high impedance (input) without much current flow.

Another example is on bidirectional serial lines where a pin can be an input and output. This allows the external chip to control its logic level when they are inputs.

 

Thank you,

Amin

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