Hello,Quartus can generate RTL view, but using its LUT as primitive. ModelSim integrated into Quartus just don’t give RTL-like view. For learning VHDL basics, is there any configuration to force either of these two software generate most simple FLIP-FLOP level schematic (like below)? https://alteraforum.com/forum/attachment.php?attachmentid=15063&stc=1 greg
I'm sorry, but are you sure you used the RTL vieuwer? I seem to remember that one uses registers, adders, comparators, muxes and logic gates in the schematic. The technology uses the LUTs.
The picture you have posted are from ISE, which is Xilinx compilation software, not Quartus.Modelsim wont give an RTL view, because it simulates your HDL code as is, it doesnt know about or care what the logic will be.
Yes I used.Is there a way to get most primitive flip-flop level logic view? Quartus post-mapping or post-fitting view all based on particular device's LUT as primitive, I wish to see more generic flip-flop gate form however.
Your code didn't have a flip flop in it. Just a latch that had to be emulated with luts. You want the map view to see the most primitive level. An FPGA is all luts and registers. That's as primitive as it gets on anfpga
--- Quote Start --- Can we get Quartus RTL views always expand thick bus lines to individual wires? --- Quote End --- In the RTL view no, but the RTL view is NOT the final implemented design. It is just your code converted to implementable hardware blocks. THe technology map view shows you each bus wire seperately and where each bit goes.