Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
1,201 Views

Generate patterns through CPLD(MAXII)?

I'm new to FPGA/CPLD. Could any one help me? 

I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. 

 

For example, under 50MHz clock, to generate pattern as "0011110000111100101010...." 

 

As I know, the CPLD/FPGAs are to be programmed as logic functions.  

Appreciate for the answers.
0 Kudos
36 Replies
Highlighted
Valued Contributor III
2 Views

Sure! This is one of the basic purposes of programmable logic. 

What you need can be done defining a simple shift register function.
0 Kudos
Highlighted
Valued Contributor III
2 Views

Thanks for promptly response, Cris! 

Then, I will need to study how to implement it through FPGA. 

 

Best regards,
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

I'm new to FPGA/CPLD. Could any one help me? 

I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. 

 

For example, under 50MHz clock, to generate pattern as "0011110000111100101010...." 

 

As I know, the CPLD/FPGAs are to be programmed as logic functions.  

Appreciate for the answers. 

--- Quote End ---  

 

 

There are two key differences between FPGAs (eg., Cyclone IV devices) and CPLDs (eg., MAX II devices); the CPLDs have a small number of logic elements and no on-chip RAM. 

 

If you are making a test pattern generator, then I would recommend looking at using a Cyclone III or IV device. The JTAG interface on the device can be used as a 'logic analyzer' (using SignalTap II) so you can see your pattern being generated, and you could wire signals from your device under test back to the FPGA to capture the response. 

 

Since the MAX II does not have RAM, this feature is not available there. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
2 Views

Dave, this is very important information to me. 

Thanks a lot for the recommendation. 

Now, I know what to start with. 

 

Best regards, 

 

Cliff
0 Kudos
Highlighted
Valued Contributor III
2 Views

Is DE0 with CyloneIII suitable for test pattern generator? 

 

Thanks.
0 Kudos
Highlighted
Valued Contributor III
2 Views

I mean the DE0 platform with followings. Will this be enough for test pattern generator? 

 

Cyclone III EP3C16F484 with ~16,000 LEs 

8MB SDRAM and 4MB Flash 

USB Blaster onboard
0 Kudos
Highlighted
Valued Contributor III
2 Views

How long is the pattern you need to generate? 

Is a fixed pattern or do you need to change it? 

In the simplest cases a CPLD would be enough: I mean if you have a medium-short fixed pattern or a well defined set of short patterns. 

The more complex is the pattern generator, the bigger the device you'll need. 

I'd suggest a device like EP3C16F484 or similar range if you want a generator with a lot of features, possibly controlled through Ethernet or serial port. 

If you instead need only a simple push-button-and-generate-pattern device, stick on a CPLD.
0 Kudos
Highlighted
Valued Contributor III
2 Views

My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.  

 

I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string?
0 Kudos
Highlighted
Valued Contributor III
2 Views

You must specify what do you mean for medium size: tens of bits, hundreds, thousands? 

The optimal solution is different in these cases. 

 

I dare say that for a pattern less than 100bits long which needs to be changed occasionally you can simply use a CPLD and the shift register solution. 

 

Usually the shift register blocks (I refer now to lpm_shiftreg) have a LOAD input which loads all data from a parallel port and/or a SHIFTIN input to load serially. 

For each clock edge, stored data is sent serially out of a SHIFTOUT port, and this is the pattern you want to generate. 

Parallel load is not convenient in your case; discard it and connect all other shiftreg input ports to external controls (push buttons, PLC or microcontroller outputs): you can do everything with these few signals. 

PLease note that minimal extra logic inside CPLD may be required if you need the pattern to be generated under particular conditions.
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

My expectation would be medium size test pattern. It won't be fixed pattern but might subject to modification while test different chips. In most cases, these patterns are not complicated.  

 

I'm checking shift register's block function, but I don't know how to generate patterns. Since normal DFF provides shift register function, how can I generate an input string? 

--- Quote End ---  

Here's what I'd do with a DE0-nano (DE0, DE1, DE2, ...); 

 

1) Use the JTAG-to-Avalon-MM master interface to provide host-to-FPGA communications. (I'm finishing off a tutorial on how to do this, I'll post it soon). 

 

2) Use a dual-ported RAM, with one side mapped as a Avalon-MM slave, and the other side connected to your test pattern logic; the test pattern logic would read a parallel word from RAM, and then write that to I/O pins, or shift it, or whatever you need it to do. 

 

3) Have an Avalon-MM slave for some control registers, to enable your test pattern generator, and monitor when it is done (or your test fails). 

 

4) Wire up your test pattern pins to the device under test, and wire response pins back to your DE0-nano. 

 

5) Either capture the response in RAM, or use a Signal Tap II instance. 

 

This is basically what I use for testing transceiver interfaces on the Stratix IV GX devices. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

You must specify what do you mean for medium size: tens of bits, hundreds, thousands? 

The optimal solution is different in these cases. 

 

I dare say that for a pattern less than 100bits long which needs to be changed occasionally you can simply use a CPLD and the shift register solution. 

 

Usually the shift register blocks (I refer now to lpm_shiftreg) have a LOAD input which loads all data from a parallel port and/or a SHIFTIN input to load serially. 

For each clock edge, stored data is sent serially out of a SHIFTOUT port, and this is the pattern you want to generate. 

Parallel load is not convenient in your case; discard it and connect all other shiftreg input ports to external controls (push buttons, PLC or microcontroller outputs): you can do everything with these few signals. 

PLease note that minimal extra logic inside CPLD may be required if you need the pattern to be generated under particular conditions. 

--- Quote End ---  

 

 

Chris, 

1. It might be hundreds of bits for a input string. 

2. Is it must to use external controls (push buttons, PLC or MCU outputs)? Can I input the string simply from the master (laptop)?  

 

Thanks!
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

Here's what I'd do with a DE0-nano (DE0, DE1, DE2, ...);  

1) Use the JTAG-to-Avalon-MM master interface to provide host-to-FPGA communications. (I'm finishing off a tutorial on how to do this, I'll post it soon).  

2) Use a dual-ported RAM, with one side mapped as a Avalon-MM slave, and the other side connected to your test pattern logic; the test pattern logic would read a parallel word from RAM, and then write that to I/O pins, or shift it, or whatever you need it to do.  

3) Have an Avalon-MM slave for some control registers, to enable your test pattern generator, and monitor when it is done (or your test fails). 

4) Wire up your test pattern pins to the device under test, and wire response pins back to your DE0-nano. 

5) Either capture the response in RAM, or use a Signal Tap II instance. 

This is basically what I use for testing transceiver interfaces on the Stratix IV GX devices. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

 

Thanks for the suggestion, Dave. 

This means that I have a lot of things to learn.  

I can have 8Mbits SDRAM from DE0 board, but I don't know if this is dual-port. Also, I need to purchase Avalon-MM IP. Right? 

 

Regards,
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

 

I can have 8Mbits SDRAM from DE0 board, but I don't know if this is dual-port. Also, I need to purchase Avalon-MM IP. Right? 

 

--- Quote End ---  

 

 

I don't think you'll need to use the off-chip RAM unless your patterns are really long. If they are, then no problem, you can use the SDRAM controller provided by Altera, and a DMA controller within the FPGA to stream from the SDRAM controller to a FIFO target, and the other side of that FIFO can be your test pattern logic generator. 

 

If you need random patterns then you can use a linear feedback shift register to do the job: 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

Chris, 

1. It might be hundreds of bits for a input string. 

 

--- Quote End ---  

 

Then you definitely need a FPGA. 

 

 

--- Quote Start ---  

2. Is it must to use external controls (push buttons, PLC or MCU outputs)? Can I input the string simply from the master (laptop)?  

 

--- Quote End ---  

 

Using buttons or generic I/Os was only an idea for a very simple solution. 

Sure you can do it with a laptop! 

For example you can send the pattern and control the generator with the RS232 serial port. 

The jtag interface solution suggested by Dave is also good, but this can be used if you only need the pattern generator connected to your laptop. If you plan to deploy the design in a commercial board, you must provide a standard widely used interface: 

in this case, besides RS232 you can implement virtually everything with fpga, from PCI to Ethernet, USB and so on.
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

Then you definitely need a FPGA. 

 

 

Using buttons or generic I/Os was only an idea for a very simple solution. 

Sure you can do it with a laptop! 

For example you can send the pattern and control the generator with the RS232 serial port. 

The jtag interface solution suggested by Dave is also good, but this can be used if you only need the pattern generator connected to your laptop. If you plan to deploy the design in a commercial board, you must provide a standard widely used interface: 

in this case, besides RS232 you can implement virtually everything with fpga, from PCI to Ethernet, USB and so on. 

--- Quote End ---  

 

 

Thanks, Cris! 

Ok, I will switch my platform from CPLD to FPGA. And I prefer to have USB as the interface input string from laptop. Ecexpt DE0 board, what Kinds of hardware or IPs I should prepare to implement the test pattern generator? 

 

My target: To have simple access to MCUs, in which, most of them are ARM based. 

1. Enter some low power modes of MCUs 

2. Access to their embflash memory, however, simple access would be enough. 

 

Best regards,
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

 

Ok, I will switch my platform from CPLD to FPGA. And I prefer to have USB as the interface input string from laptop. Ecexpt DE0 board, what Kinds of hardware or IPs I should prepare to implement the test pattern generator? 

 

--- Quote End ---  

Provide a better description on what the patterns are supposed to be and we can provide a better answer. For example, do you have hundreds of individual bits/wires that you need to generate patterns on, are the patterns all the same, what frequency do you need to generate the patterns at? 

 

 

--- Quote Start ---  

 

My target: To have simple access to MCUs, in which, most of them are ARM based. 

1. Enter some low power modes of MCUs 

2. Access to their embflash memory, however, simple access would be enough. 

 

--- Quote End ---  

The ARM MCUs already come with these features, why do you need an FPGA? 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

Provide a better description on what the patterns are supposed to be and we can provide a better answer. For example, do you have hundreds of individual bits/wires that you need to generate patterns on, are the patterns all the same, what frequency do you need to generate the patterns at? 

 

The ARM MCUs already come with these features, why do you need an FPGA? 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi Dave, 

Just as what you mentioned, MCUs provide all the access to these functions. But I don't have their EV boards. It's quite embarrassing that sometimes I have to debug those MCUs during it's development stages. In most cases, low power leakage and flash access are the problems I see. These are not my own product, however, I sometimes been asked to do so. As a result, I won't have EV board to test them. And I am thinking about how to create a platform in order to have direct access to these MCUs. I know it's strange, but it's a problem to me now. 

 

I wastold that it can be down with FPGA platform. That's why I'm here.
0 Kudos
Highlighted
Valued Contributor III
2 Views

 

--- Quote Start ---  

 

I am thinking about how to create a platform in order to have direct access to these MCUs. 

--- Quote End ---  

 

 

What do you mean by 'direct access'? You commented on accessing the flash on these devices, but the flash is internal. The only way to get to the flash is via the JTAG port on the device, and while you could implement that using an FPGA, what is the point, just buy a cheap JTAG interface. 

 

Perhaps you could clarify what you want the FPGA to be able to do to the microcontroller. 

 

Cheers, 

Dave
0 Kudos
Highlighted
Valued Contributor III
2 Views

Hi Dave, 

Sorry to let you wait.  

 

I need to correct my statement. 

1. My intention is to have simple test to microcontrollers (not specific one). For ex. Idd/power consumption, flash operation. 

2. Some MCUs are not desgined with JTAG interface for test but they have similar serial interfaces (may be some specific protocols) that I have to deal with. Each one might be different. 

3. As a result, I plan to use FPGA to generate patterns to access the chips. The patterns that I need to geneate would around be 2-10 pins. And there will be up to 10~30 types of patterns for each pin to enter test mode and setup control signals.  

 

As a result, I need to make up my mind: 

1. Which FPGA/CPLD would be suitable for me 

2. How to generate patterns, simply through shift registers and input patterns from my laptop? 

 

best regards,
0 Kudos