Generating an Intel Agilex per pin RLC IBIS (.ibs) file

[EPedersen]

Hi,

We're trying to produce an ibis file for our FPGA design using the method outlined in:
Generating an Agilex per pin RLC IBIS (.ibs) file (intel.com)

We require the per-pin package RLC data for the A5ED065BB32AES in order to finish our testing.

Thanks!

[AqidAyman_Intel]

Hi,

Thank you for reaching out FPGA Community!

Please allow me some time to check on this for Intel Agilex 5 device. I will update you later.

Regards,

Aqid

[AqidAyman_Intel · Accepted solution]

Hello,

I got update from the internal team on this request.

For your information, the IBIS Writer support for Agilex 5 is same as Agilex 7 which it has been available through script since 23.1. Customer can generate the design specific IBIS models with per pin RLC by using the script. 

You may refer the Quartus Prime Pro Edition User Guide: PCB Design Tools through the link below for more info of the IBIS Writer support for the Agilex devices. As per the UG, you have to refer to the README.txt file for the complete instruction of using the script. I would recommend you use the IBIS Writer script of the latest Quartus version.

https://www.intel.com/content/www/us/en/docs/programmable/683768/23-1/ibis-model-access-and-customization-flows.html

Regards,

Aqid

[EPedersen]

Thanks Aqid for your help!

-Erik

[AqidAyman_Intel]

Hi Erik,

I’m glad that your question has been addressed, I now transition this thread to community support.

p/s: If any of the answers from the community or Intel Support are helpful, please feel free to rate a full score for the evaluation survey. I really appreciate your kindness.

Regards,

Aqid