I am currently using an Cyclone 10 LP in Quartus 18.1 with an EPCS16 device for configuration for FPGA and NIOS II application.
This is basically working with the legacy Serial Flash Controller Intel FPGA IP.
Unfortunately this IP no longer supports the deactivation of the dedicated Active Serial Interface.
Since the design has a second SPI Slave on this very same (dedicated) SPI bus, I need to access these pins from the topmodule.
So i tried using the Generic Serial Flash Interface IP instead, which support the deactivation of the dedicated interface.
On the first try, even without deactivating the dedicated interface.
With this IP, Nios no longer provides the mem_init_generate script to generate the hex file for the Nios application.
When I manually generate this hex and the programming file Nios does not boot.
It seems, that by using this IP the Memcpy based bootloader from Nios or the access to the flash device in general is not working.
Is there any point I am missing, or is there another IP that I can use?
The IP the support disable dedicated Active Serial Interface are:
- Intel FPGA Generic QUAD SPI Controller II Core
- Generic Serial Flash Interface IP (GSFI IP)
However, Intel FPGA Generic QUAD SPI Controller II Core did not support EPCS flash device
Unfortunately, the only choice you have is GSFI IP.
First, you need to change "Write Instruction Register" in GSFI IP...
EPCS device does not support "Read Flag Status Register" (70h).. You need to change it to "Read Status"(05h)..
- Open GSFI IP --> make sure your mouse cursor in red circle (refer picture below) --> then, right click --> choose Show Hidden Parameters.
- Change Write Instruction Register from 0x00007002 to 0x00000502
If the above solution did not help, please let me know how you manually generate this hex in details.
thank you for answer. I was able to test this with the new Write Instruction value, but it is not yet working.
I connected the atom ports of GFI IP to the EPCS device by using the index 0 of the vectors for dataout and datain. Is this connection scheme correct?
For the manual hex file generation, i used the command, that the mem_init_generate command executes when a Serial Flash Controller is instantiated.
alt-file-convert -I elf32-littlenios2 -O hex --input=../software/cpu/cpu.elf --output=cpu.hex --base=0x00600000 --end=0x007fffff --reset=0x00723000 --out-data-width=8 --boot=C:/intelfpga/18.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec
The module's base adress is 0x00600000 and the reset offset vector is 0x123000.
Do I need another bootloader for this configuration?
Is there a detailed documentation on this GSFI IP?
Thank you for your help.
I'm sorry for late reply.
Regarding to your sentence "using the index 0 of the vectors for dataout and datain", can I get further explanation? I didn't get you here.
I think before testing the booting, I need to get the confirmation from you whether you are able to access the flash with GSFI or not?
Have you tried read flash ID or do simple read & write to flash using GSFI? everything is working fine?
This to make sure the hardware connection is working.
It has been a while since you have posted an update to this Case. Do you have any update to me? Kindly get back to me if you still need my assistance.