Gigabit Ethernet using FPGA in cyclone 5 De10 nano board

[Manav]

I am using the cyclone 5 DE10 nano board. Is there any way I can connect the ethernet PHY to the FPGA using the TSE IP? Can the pins be shared between the HPS and the FPGA?

[Deshi_Intel]

Hi,

FYI... Intel FPGA forum community is meant to support dev kit board developed by Intel only and not for 3rd party vendor board like this DE10-Nano board which is development by Terasic

• I recommend you to checkout DE10-Nano board website for more info and reference design
• https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=4
• You can also email Terasic for support enquiry - support@terasic.com

1. Is there any way I can connect the ethernet PHY to the FPGA using the TSE IP ?

• I can comment TSE IP do support RGMII interface but I am not familiar with the PHY chip on DE10-nano board.
  • Feel free to contact terasic directly to check out with them

1. Can the pins be shared between the HPS and the FPGA ?

• No, Cyclone V SOC HPS has its own dedicated IO pins while FPGA has its own dedicated IO pins

Thanks.

Regards,

dlim