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Glitch on DCLK during Active Serial Arria 10

BenUhing
Beginner
276 Views

I have a PCB with an Arria 10 that I'd like to support both passive serial and active serial config. I can successfully configure the Arria 10 via JTAG and passive serial, but I cannot successfully program the flash (Micron MT25QU512ABB8ESF) and boot in active serial mode.

To achieve this, I have a switche on the MSEL pins and have been trying to change them from MSEL{2,1,0} = 0,0,1 for Passive Serial and 0,1,1 for Active Serial. I also have a buffer IC (TI SN74AUC2G126) connected to a switch to allow DCLK to be either an input to or output from the Arria 10.

Looking at DCLK output with the Intel flash loader bitstream loaded via JTAG, I see a glitch on DCLK - see attached scope grab. After the flash loader program completes, it fails to verify. If I try to boot anyway, the nStatus toggles and the part starts trying to configure again. I assume this glitch on DCLK is causing my problem?

The scope grab is with infinite persistence on. The glitch moves around the high side of the clock signal. There are some clock pulses that do not have a glitch.

I have tried removing the buffer so that DCLK is only an input into the Arria 10 to remove propagation delays, but that hasn't removed the glitch on DCLK. I have inspected VCC (0.95 V), VCCH_GXB{L,R}, VCC_PLL, and VCCPGM (all 1.8V) with a differential probe at vias on the back of the FPGA and do not see any noise on the power rails.

When configured via JTAG or Passive Serial with our bitstream, all other aspects of the system work as expected, even when testing across in-spec voltage and temperature variations, including 6.25 GHz transceivers and 2000 MT/s DDR4 memory controller.

Any suggestions about how to configure via Active serial would be greatly appreciated! Thanks.

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7 Replies
JohnT_Intel
Employee
206 Views

Hi,


May I know if you change the MSEL after the FPGA is power up or before it is power up? If you change the MSEL after the FPGA is power up then I do not think you will be able to use Active Serial as the MSEL setting is only read during power up.


BenUhing
Beginner
201 Views
John,

Thanks for responding. We won’t need to hot switch MSEL after power up. I’m only changing the position of the switch before power up.
JohnT_Intel
Employee
197 Views

Hi,


May I know if there is a reason that you are using a buffer switch to connect the DCLK signal? I suspect that your U503 device is causing the glitches.


If you look into Intel Arria 10 Development kit, we do not use any buffer or switches for the DLCK and just connect DCLK to both Passive Serial and Active Serial device directly. You may refer to https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/FPGA/A10GX_PCI....


BenUhing
Beginner
192 Views
That’s good to know. I will remove it from future revisions. However, I have depopulated the buffer from my PCB and run a short wire across its pads connecting DCLK to AS_DCLK and the glitch is still there. Can you think of anything else that might be causing it?
JohnT_Intel
Employee
178 Views

Hi,


Not sure if this is due to your board trace? Have you check if there is any distortion that cause the issue?


BenUhing
Beginner
173 Views

John,

It might be, but I have tried to eliminate the possibility. I have attached a screen grab of the layout. The purple vias are at the back of the Arria 10. R638 is the 22 ohm series termination resistor. I have tried removing R638 and installing a 1k ohm resistor from DCLK at the right pad of R638 to ground. I can still see the glitch with just 330 mils of trace.

What is the source of the output clock on DCLK when programming a flash and trying to boot from one using Active serial? Is it the internal oscillator or is it dependent on CLK_USER? I also have other differential clocks input to IOs, but I don't think the flash loader design has any way of knowing they're clocks before configuration.

If it matters, we're using the 10AX090N2F40E2SGJZ.

JohnT_Intel
Employee
158 Views

Hi,


When you are programming the flash from FPGA, the DCLK is coming from FPGA internal clock.


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