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Global Resets and Active High or Active Low

joe306
New Contributor I
167 Views
Hello, is there any recommendations on whether to use a Active High or Active Low Reset and using Global Resets? Some say minimize the number of resets in the FPGA design. Thank you
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1 Solution
Ash_R_Intel
Employee
154 Views

Hello,


Here is an Application Note providing recommendations on how reset should be applied to the design.

AN 917: https://www.intel.com/content/www/us/en/programmable/documentation/ezg1603893811352.html


In brief, guideline that I follow in my design:

1) Reset should be asynchronously applied to the sequential elements.

2) Deassert the reset synchronously with the clock of the target flop. This means that each clock domain in the design should have its own reset which gets asserted asynchronously, but deasserted synchronously with the clock. These resets should be internally generated from the master reset. Check Reset Release IP.

3) Not all the registers in a pipeline are required to be have a reset pin connected, but the main reset should remain asserted for sufficient number of clocks so that it propagates to all the flops in the pipeline with the clock. Note that there will be dependency on the clock here. More details in AN 917.

4) There should be a synchronizer circuit deployed so that the impact of metastability is removed. You may use the Reset Release IP for this purpose.

5) Generally, first flop and the last flop in the pipeline are recommended to have a reset pin, so that the output goes to a known state immediately when reset is asserted. More details in the AN 917.

6) Active high or active low depends on the functional and the power requirements of the design. Active high reset consumes less power as in the inactive state 0V has to be supplied.

7) Constraints are another important things. Refer AN 917.


Regards.



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1 Reply
Ash_R_Intel
Employee
155 Views

Hello,


Here is an Application Note providing recommendations on how reset should be applied to the design.

AN 917: https://www.intel.com/content/www/us/en/programmable/documentation/ezg1603893811352.html


In brief, guideline that I follow in my design:

1) Reset should be asynchronously applied to the sequential elements.

2) Deassert the reset synchronously with the clock of the target flop. This means that each clock domain in the design should have its own reset which gets asserted asynchronously, but deasserted synchronously with the clock. These resets should be internally generated from the master reset. Check Reset Release IP.

3) Not all the registers in a pipeline are required to be have a reset pin connected, but the main reset should remain asserted for sufficient number of clocks so that it propagates to all the flops in the pipeline with the clock. Note that there will be dependency on the clock here. More details in AN 917.

4) There should be a synchronizer circuit deployed so that the impact of metastability is removed. You may use the Reset Release IP for this purpose.

5) Generally, first flop and the last flop in the pipeline are recommended to have a reset pin, so that the output goes to a known state immediately when reset is asserted. More details in the AN 917.

6) Active high or active low depends on the functional and the power requirements of the design. Active high reset consumes less power as in the inactive state 0V has to be supplied.

7) Constraints are another important things. Refer AN 917.


Regards.



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