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Valued Contributor III
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Global Variables in VHDL

Hello, 

 

I am told that the 2008 VHDL allows one to use global variables. Does anyone have nay example code that would demonstrate this? I am interested in any kind of feedback I can get from the development community regarind their use. 

 

Thanks  

 

Bill
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Valued Contributor III
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Re: Global Variables in VHDL

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Valued Contributor III
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Re: Global Variables in VHDL

Do you mean global signals? I've heard of this too and thought someone told me they had it working, but I never tried it. I'd also be curious if there's anything similar for Verilog? I think it's a very dangerous tool, as the lazy engineer could start passing new signals around globally rather than modifying all the port lists, component declaration, but I think that would make debug extrenly difficult. But I think it would be fantastic for debugging, temporarily getting signals from other hierarchies, and could probably be used for general coding if well disciplined. (I'd also be curious if it works with Incremental Compilation?)

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Valued Contributor III
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Re: Global Variables in VHDL

Global signals and global shared variables have been around since the dawn of VHDL I think (at least since 93). They allow you to put a signal/shared variable in a package. This signal/variable is then accessible/modifiable to all code that use the package. 

 

This feature is only meant as a debugging tool. So much so that altera refuse to compile global signals. They know about them but will not allow their compilation. 

 

Are you sure you're not thinking about accessing things heirarchically? in 2008 you can access signals/variables without having to send them through port maps, but again, its only meant for debugging.
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Valued Contributor III
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Re: Global Variables in VHDL

Basically I'm trying to keep track of how many time state machines are run from start to begining on a number of different levels. I felt a global variable (although frowned upon) may be an easy solution.

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Valued Contributor III
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Re: Global Variables in VHDL

if its for simulation, then theres no problem, and encouraged. You can use the heirarchical access (added in VHDL 2008) to get at them all from the testbench, so theres no need to modify your code. You will need modelsim 10+ though. 

 

If its for inside an fpga - impossible. You'll need to do things properly and pass all the information through the port maps.
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Valued Contributor III
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Re: Global Variables in VHDL

What actually is this concept of "global signal" ? We use generics to pass info to anywhere in the design. For opposite side i.e. for a signal to be driven by any logic anywhere then we already have examples of read buses such as nios read data but in this case some logic is needed to prevent bus contention.

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Valued Contributor III
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Re: Global Variables in VHDL

a global signal is modifiable by anything that can see it. a generic is just a constant.

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Valued Contributor III
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Re: Global Variables in VHDL

I should have added to generic any input that goes anywhere e.g. write data of nios. I am still vague about the concept of global signal despite the excitement.

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Valued Contributor III
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Re: Global Variables in VHDL

 

--- Quote Start ---  

 

i have the following (maybe strange) problem: 

My design is very modular and will be configured by a setup file 

(pkg)! This setup file defines wether specific modules are generated 

or not. 

For a special reason only the generated modules should now become an 

individual (increasing) number as an address, e.g. in a generic! This 

is only for configuration!! 

I am thinking of a kind of a function with a "Global Variable" there, 

which is intialized (to 0) at the beginning and increased by one every 

time a module is instanciated (the function called)!! This is easy in 

a procedural language but i can not find any construction in VHDL, 

which could do this. 

--- Quote End ---  

Rather than having your generic values hard-coded by storing them in a package, use the Quartus and Modelsim Tcl scripting capabilities to set generics inside a loop. 

 

For example, I have a board with four identical FPGAs. The FPGAs get programmed with a device ID (0 to 3) and that device ID is compared to a pin strapping device ID (also 0 to 3). In the unlikely event that I concatenate the RBF files in the wrong order, and hence program the wrong FPGA with the wrong image, then the device ID check will fail, and the boards will not enable their I/O drivers, avoiding the potential for I/O driver conflicts. 

 

The Tcl script goes something like this; 

 

1) Get the current OS timestamp 

 

2) for {set i 0} {$i < 4} {incr i} { 

* set the device ID generic to i 

* set the timestamp generic 

* synthesize 

* copy the RBF to a unique name 

 

3) Concatenate RBF files into a single image for download via FPP configuration. 

 

If you have a design where you want to track how many of something are instantiated, then you could use Tcl variables to track the start index and number used by a particular design instance, and continue to track the number through what I assume are multiple synthesis runs. 

 

Cheers, 

Dave
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Valued Contributor III
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Re: Global Variables in VHDL

 

--- Quote Start ---  

I should have added to generic any input that goes anywhere e.g. write data of nios. I am still vague about the concept of global signal despite the excitement. 

--- Quote End ---  

 

 

Just to clear this up, here is a global signal,  

 

library ieee; use ieee.std_logic_1164.all; package my_pkg is signal global : std_logic; end package my_pkg;  

 

Now any enttity that includes "my_pkg" can read and modify the signal "global"
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