Guidance on Optimizing FPGA Design for Better Performance

[alyxbond]

Hello Intel Community,
I’m currently working on an FPGA design and looking for some advice on optimization techniques to improve performance and resource utilization. Specifically, I’m working with Intel’s programmable devices, and I would love to hear about best practices, tools, or methodologies that have helped others. Any suggestions for improving synthesis and timing closure would be greatly appreciated.
Thanks in advance for your insights!

[sstrell]

Start with the user guides written for this (Design Recommendations, Design Optimization): https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html

Then take a look at training.  There are many self-paced eLearnings as well as free instructor-led classes on these topics: https://learning.intel.com/developer/pages/128/intelr-fpga-training