H-tile Hard IP Fitter Failed in Stratix10mx

[clair]

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_CR2_EHIP_CORE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 HSSI_CR2_EHIP_CORE, which is within H-Tile Hard IP for Ethernet Intel FPGA IP ex_100G_alt_ehipc2_1920_ia42rui.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_CR2_EHIP_CORE name(s): u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|c2_ehip_core_inst
Error(16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between the HSSI_CR2_EHIP_CORE and destination HSSI_ADAPT_RX
Info(175027): Destination: HSSI_ADAPT_RX u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_adapt_rx.inst_ct1_hssi_adapt_rx
Error(175022): The HSSI_CR2_EHIP_CORE could not be placed in any location to satisfy its connectivity requirements
Info(175021): The HSSI_ADAPT_RX was placed in location HSSIADAPTRX_1T1F0
Info(175029): 3 locations affected
Info(175029): HSSICR2EHIPCORE_1TL1
Info(175029): HSSICR2EHIPCORE_1TR0
Info(175029): HSSICR2EHIPCORE_1TR1
Error(175006): There is no routing connectivity between the HSSI_CR2_EHIP_CORE and destination HSSI_ADAPT_RX
Info(175027): Destination: HSSI_ADAPT_RX u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[2].s10_xcvr_native_inst|s10_xcvr_native_phy|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_adapt_rx.inst_ct1_hssi_adapt_rx
Error(175022): The HSSI_CR2_EHIP_CORE could not be placed in any location to satisfy its connectivity requirements
Info(175021): The HSSI_ADAPT_RX was placed in location HSSIADAPTRX_1T1F4
Info(175029): 1 location affected
Info(175029): HSSICR2EHIPCORE_1TL0

I generated a 100G H-tile Hard IP for Ethernet Intel FPGA IP, and called it twice as u_0 and u_1, but when I compile the project, 

[Deshi_Intel]

HI,

Can you share with me your Quartus project archived file so that I can review your design to root cause the fitter error ?

Thanks.

Regards,

dlim

[clair]

Hi,

   Here is my project, looking forward to your reply.

Best Regards

[Deshi_Intel]

Hi,

I suspect fitter error is just due to some channel pin placement issue and not about Quartus design connection or RTL error.

This is due to once I disable your pin location setting in your Quartus project (let Quartus auto fit pin placement) then fitter compilation can passed.

• I didn't check all your pin placement vs Quartus compilation passed pin placement yet but at high level I can see that your bank 1F Rx{3:2] location is swap.

I encourage you to do the same like me. Let Quartus auto fit then compare with your original pin location setting then you will figure out which pin placement is causing the problem here

Thanks.

Regards,

dlim

[clair]

hi，

[clair]

Hi,

I just set the pin placement as the schematic said. Now I suspect the sdc file about the native phy clk has problems. Which files should I refer to to place the RX_CLK* and TX_CLK* in the right channel?

The sdc in the project is auto generated by the htile IP.

set RX_CLK0 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set RX_CLK1 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set TX_CLK0 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[0].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]
set TX_CLK1 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[1].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]

set RX_CLK2 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[2].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set RX_CLK3 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[3].s10_xcvr_native_inst|*rx_pcs_x2_clk|ch0]
set TX_CLK2 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[2].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]
set TX_CLK3 [get_clocks u_0|av_top|alt_ehipc2_0|alt_ehipc2_hard_inst|altera_xcvr_native_inst|g_native_phy_inst[3].s10_xcvr_native_inst|*tx_pcs_x2_clk|ch0]

[Deshi_Intel]

Fitter passed design QAR file

[Deshi_Intel]

Fitter error explanation analysis 

[Deshi_Intel]

HI,

Perhaps my explanation is not clear to you. let me explain again.

Fitter compilation error happen because In Bank 1F, you placed TxRx_serial_0[3] pin in location of TxRx_serial_0[2] pin and vice versa.

• Attached is the S10 pinout excel file that show you the pin location that caused the fitter error. (refer to column highlight in red)
• I also attached fitter passed design QAR file for your reference.

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi,

I hope my explanation of fitter error and resolution on Nov 30 is clear to you.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim