HDMI Output with Cyclone IV

[Altera_Forum]

Hello, i was looked at the forum and could not find this answer.  

 Is it possible to drive an HDMI port directly from a Cyclone IV as it is possible with Xilinx Spartan 6?  Regards,  LR

[migry_tech]

Good question.

I have experimented with the well known code created by "hamster" in New Zealand on Spartan6 and Artix7 devices and had success at various resolutions up to 1080p60.

I am now designing my own FPGA board, a mk2. The mk1 was based around a Cyclone II QFP. I really need more memory or more pins to interface to a fast SRAM. I am considering the Cyclone IV. I want to add a HDMI connector for video, so I am interested if this can be achieved on a cheap Altera part. Since I already have a cheap Chinese "ZR-Tech" development board, just yesterday I was researching the answer to your question.

I did find that someone had re-implemented the "hamster" code on a Cyclone. I forget where I downloaded the source code ZIP, but in the header I see the name "D. Beesley".

The ZR-Tech board has an expansion connector but the pins are shared with the VGA. It took a while to figure out if there were some differential outputs which could be used. I found 3 pairs. The last pair took one pin from the connector and another from the clock pin of the FPGA, to which I connected with a flying wire held manually.

I was also using a Numato HDMI PMOD PCB which has some kind of buffer IC.

I couldn't select LVDS in the pin planner, so I had to select something like LVDS_E_3R. I may be driving the outputs with too high a swing, I'm not sure.

To my amazement (after a little fiddling) I got a picture. It's 480p60.

So I wanted to see if I could port my own Verilog code (derived from "hamster"s VHDL. The Xilinx parts have a hardware SERDES, but the ALT_LVDS (?) Megafunction appears to be created from ordinary gates. I used this to replace the SERDES in the Serialiser_10_to_1 source code module. I did some Modelsim simulations and the waveforms did appear to be correct.

I got a stable picture on the Dell monitor, but the picture was a set of vertical lines and not a band of colours. So that is still to be debugged.

I would like to try 720p and 1080p, but I do not know how fast the differential IO pins which I am able to use are. In fact I am completely confused as to which pins on the EP4C6E are high speed and which are not. The pin planner doesn't help. It allows me to choose pins and then complains during compilation. If my new FPGA board uses a Cyclone IV I really want to choose the correct pins and this might even mean using a VCCIO of 2.5V for that bank. That's if there is a bank with 4 sets of high speed differential. I really can't waste any pins.

PM me and I can send the working source code.

--migry