I was trying to use DDR3 with Uniphy on Cyclone V GT Develpoment Board for my design. The DDR3 model is Micron's MT41K128M16JT-125.
When I made a simple controller on avalon and test design for DDR3 which includes a pll with 1 in_clk and 1 out_clk, there was no problem. (Shown on figure)
But when I pluged-in this controller to my design which includes a pll with 1 in and 3 out clocks, i got calib_fail. (Shown on figure)
(There are fifos to save data between cross clock domains
What can be the problem and its workaround?
Thanks for providing detail diagram drawing. This is good in analyzing issue debug.
FYI... DDR3 calibration only rely on operation between UNIPHY IP and on board DDR3 SDRAM.
Therefore, I suspect DDR3 calibration failure could be due to either
I am not worry about the DDR3 setting now as you used the same DDR3 setting and it passed calibration in original design, right ?
Your goal now is to take the calibration failing design and gradually remove additional design block one by one to make it more alike to original passing design.
Then eventually you will figure out which part of the design is causing the problem here.
I have not hear back from you for 2 months. Hopefully my debug suggestion help out and you are able to make progress with your project.
For now, I am setting this case to closure.