In most eval boards of Cyclone 5 Soc I have seen, they generate the 25 MHz HPS_CLK1 and HPS_CLK2 from a chip that has one input clk pin and multiple output clock pins. Some of the chip outputs are clocks for the FPGA and some other components on the board. My board won't have other components. Input clk of 50MHz will be input for the board. This 50MHz will be an input to the FPGA. Can I just use a separate crystal oscillator of 25MHz and connect its output to both HPS_CLK1 and HPS_CLK2?Thanks
I believe you can but there is a jitter requirement for the HPS PLL Input (refer to https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf page 53). Also note that some peripheral (USB, Ethernet) may require you to supply an external clock of certain frequency to the PHY or the SoC chip (depending on mode).