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New Contributor II
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HPS & FPGA boot independently

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Hello,

 

We are booting FPGA and HPS independently from each other, i.e. each side is responsible only only for itself.

But I have some misunderstanding of this concept.

 

But HPS is configured as part of qsys (HPS' SDRAM for example), which means that FPGA configuration much starts first before HPS boot, Right ?

 

Is that what happens when they start independently, i.e. FPGA is configured before HPS ? How ?

 

Thanks

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Employee
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Hello Ran,

Yes you can. You need to get the uboot and preloader separately from yocto project compilation. Also make sure to keep device tree (dtb) clear from any FPGA related device.

 

HPS will help you to configure the pins, HPS-FPGA bridges, and help you to generate preloader and uboot later in SoC EDS.

Hope this might help.

 

thanks

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Employee
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Hello sir,

FPGA in SoC devices can be configured in four different levels:

1- Preloader (except Arria 10 SoC).

2- U-boot.

3- Linux Kernel.

4- independently from Flash configuration device.

 

Most of the cases, it is recommended to have FPGA configured before Linux boots, specially when there are shared pins through FPGA.

 

The HPS IP in Platform Designer is not the real ARM processor. ARM is hard-coded. this IP is used for some configuration tweaks, which are used to generate the preloader and uboot (the way your system will behave).

 

Our recommended flow to overcome this issue is to configure the FPGA before Linux. Most of our reference designs are commonly using MMC.

 

To be familiar with other FPGA configuration approach, you can refer to this link:

 

https://rocketboards.org/foswiki/Documentation/GSRD131ProgrammingFPGA

 

Hope this might help.

Thanks

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New Contributor II
79 Views

Hi,

 

Thank you very much for the answer.

In our configuration there is no interaction between fpga and hps, (so fpga is configured independently from flash configuration device).

In such configuration, can I assume that even if I does not configure hps in platform designer, it should startup correctly ?

 

Thanks,

Ran

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Employee
80 Views

Hello Ran,

Yes you can. You need to get the uboot and preloader separately from yocto project compilation. Also make sure to keep device tree (dtb) clear from any FPGA related device.

 

HPS will help you to configure the pins, HPS-FPGA bridges, and help you to generate preloader and uboot later in SoC EDS.

Hope this might help.

 

thanks

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New Contributor II
79 Views

Hi Fawaz,

 

One more on this issue if I may, does preloader configured sdram according to configuration of HPS in platform designer ? If so, doesn't it mean that a yocto preloader might not be suitable for a specific sdram-hps,?

I ask just to be sure I understand it.

 

Thanks!

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Employee
79 Views

Hello sir,

Yes, you are right, sdram, clocking, pin muxing and IOCSR all all handled by preloader. You need to take care of them:

https://rocketboards.org/foswiki/Documentation/PreloaderUbootCustomization131

 

Thank you.

 

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Beginner
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Hello i have a similar question may be someone can help me out.
We have a custom board and it has a CYCLONE V 5CSEBA5U23I7 on it.

on our custom board the HPS and the FPGA share the reset pin. both are getting the power on reset from the same source at the same time. e.g. when i switch on the FPGA boots from its own QSPI and the HPS loads the preloader from its own QSPI. both are power on independently.

i am not sure how to make the power on sequence.

the FPGA must need to boot first from the HPS if i am using H2F master and H2F lw bridge in the FPGA?

Here is what happens. when i power on my device i see that the H2F master and H2F lw bridges are not initialized automatically by the HPS. Although they exist in my QSYS project.

Then i manually initialize both bridges manually in the baremetal application in HPS firmware.

socfpga_bridge_setup(ALT_BRIDGE_LWH2F);

etc..

Now if i flash my program on the HPS and do a power on. the program on the HPS traps. and i think it traps because it does not see the H2F bridges.

but if i flash the *.sof on the FPGA and then start my HPS then every thing works perfect.

is there any one who can suggest me what should be the power on sequence required if i want to use the resources of the FPGA on the HPS?



many thanks.
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