Hard Lock of Logic Cells - Cyclone V

[Tom_BGU]

Hello all,

How can I hard-lock specific logic cells and set the interconnection manually? 

For example, two LCELL cells which I want to be as close as possible to one another without changing their location between compilations?

Thanks,

Tom

[Tom_BGU]

1.Assignment editor --> to --> Choose a sample cell (like a delay-element) --> Assignment name --> Location --> Value: LABCELL --> Insert Coordinates --> Compile
2. Open Chip planner --> Make sure this cell is well placed
3. Project --> Generate .tcl file 'XXX_tcl_v1' (save at output_files)
4. Open generated file
5. Update the rest of the cells accordingly
6. delete unecessary line from the addign_editor
7.tools --> tcl scripts --> run

[Kenny_Tan]

you can only lock the ALM but not routing. we are sorry to inform this.

[Kenny_Tan]

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.