Hello everyone, I need your help I'm using ADC AD9254 and DAC 5672, with FPGA DE10 standard, I want to acquire data, so Implement this code: the data out is associated to The dac, I get the result below:

[JEL_W]

LIBRARY ieee; 

USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY Co IS 

port (clk:    in std_logic;

   reset:   in std_logic;

   DCO:    in std_logic; 

Data_valid: out std_logic;

Data_in:  in std_logic_vector(13 downto 0);

Data_out: out std_logic_vector (13 downto 0)

);

end;

architecture Co_arch of Co is 

signal count : std_logic_vector(13 downto 0); 

begin 

process(clk,reset)

 begin

 if reset='1' then 

   count<= (others=>'Z');

 elsif rising_edge(Clk) then

 if DCO='1' then 

 count<=Data_in;

 Data_valid<='1';

 else

 count<= (others=>'Z');

 Data_valid<='0';

end if;

end if; 

Data_out<= count;

end process;

end Co_arch;

[Rahul_S_Intel1]

Hi ,

May I know what help you needed

[JEL_W]

Hi

I sent a sinusoidal signal through low frequency generator to ADC , but I didn't manage to get the same signal at the output of DAC,

I get an inversed signal, the question is how can I obtain the same signal, Did I miss something in the code ?

Thank you

[corestar]

Is your DAC exepcecting signed or straight binary. Same for the ADC. What you are seeing is almost right and very common when there is a signed unsigned conflict. For example, if your ADC is returning a signed number, but your DAC expects straight binary, but you fail to offset it, you will see something like what you show.

[IDeyn]

Hi JEL W,

It looks like you missed a sign, either in code or in DAC or ADC settings, where you probably need to choose two's complement instead of offset binary which is chosen by default.

--

Best regards,

Ivan