Help Needed: Ch7010 Tv output

[Altera_Forum]

Hi All, 

 Has anyone tried to configure the ch7010 chrontel chip for TV output mode. My system has 640x480 resolution video output in VGA mode.  But i want the output in composite video / S-video format. I am using altera 3c120 development board and for the input / output video, I am using Bitec Quad video board.   And the CH7010 chrontel chip need to be configured for TV output. I tried configuring the chip for both slave clock mode as well as master clock mode.  But in both the modes, the output video quality is pathetic with a lot of "dot-crawl effect" and mixing of chroma / luma bandwidths.   I tried setting different bandwidth settings for chroma / luma filters but have no effect on output.  Can anyone please suggest the directions to solve this problem.   The active output video resolution need to be 640 x 480. the TV output format can be anything NTSC / PAL.  Thanks in advance.   Regards, Foram

[Altera_Forum]

I am attempting this right now and having little luck. 

 Amazingly enough, I can actually see a [mangled] image when using the Bitec reference design, which supposedly outputs to a different VGA board!  When I attempt to configure the Ch7010b using the documented settings I get nothing. Any project or code showing register settings that achieves this would be greatly appreciated.  William Guynes

[Altera_Forum]

Hi, 

 Sorry for the delayed response.   here are the ch7010 settings for VGA output. These settings are for the VGA resolution output 640x480 from the DVI port.   i2c_write(base_address, 0xea>>1, 0x15, 0x00 );  i2c_write(base_address, 0xea>>1, 0x31, 0x00 ); //   i2c_write(base_address, 0xea>>1, 0x32, 0x23 ); //  i2c_write(base_address, 0xea>>1, 0x33, 0x08 ); //  i2c_write(base_address, 0xea>>1, 0x34, 0x16 ); //  i2c_write(base_address, 0xea>>1, 0x35, 0x30 ); // chrontel   i2c_write(base_address, 0xea>>1, 0x36, 0x60 ); //  i2c_write(base_address, 0xea>>1, 0x37, 0x00 ); //  i2c_write(base_address, 0xea>>1, 0x49, 0xc0 ); // Set DVI MODE   i2c_write(base_address, 0xea>>1, 0x21, 0x01 | 0x08 ); // DAC bypass  i2c_write(base_address, 0xea>>1, 0x22, 0x16 ); // BCO = VSYNC  i2c_write(base_address, 0xea>>1, 0x1c, 0x04 ); // Invert XCLK Polarity  Hope this would help.