Help for storing nios II software and fpga config in flash

[Altera_Forum]

Hi, 

 I need some help about storing fpga configuration and nios software in a extern flash.  I'm using pci dev kit from altera which has a stratix II gx, a 512 Mb CFI flash and a epm570 with a parrallel flash loader for writing configuration at start up.  I make a design with lot of IP's, glue logic and a nios processor executing software from onchip memory (M4K's RAM block). My problem is that I can convert my sof file to a pof file and write it to the flash but when the board start, my nios software doesn't run. Of course.  I read many application note about boot methods (like AN458) but I don't know how to do...  So first, I add a cfi flash controller (and a tristate bus) in my sopc system and pointing reset vector to extern flash. Generate sopc, compile new sof but it doesn't work.  When I try to program my sof and my elf with flash programmer, I've got an error "No CFI table found".  1/ I try to test hardware between nios and flash but I can't use memtest.c because my onchip memory has not enough space to compile and I can't increase it (stratix II memory is full)  2/ One problem is when I add extern flash in sopc, I tell that my address bus width is 25 bits (so 24 downto 0) and sopc generate a component with 26 bits (25 downto 0) ?? Is that a bug ?? What can I do with my additional bit.... ?   Could someone help me and give me some tips ? I'm lost and I don't know what to do... :rolleyes:   I see an another method : creating a pof including my sof configuration and my elf software program. Is that possible ? How ?  Thank you in advance for all your help!  Bye. Fabrice.

[Altera_Forum]

it is not a bug. 

26 bits are the address span for 8 bit devices (counting in bytes) 25 bits are for 16 bit devices (words)  if your cfi flash is a 16 bit type then you must not connect nios address bit 0 as this bit would always be 0 due to 16bit accesses and so no odd addresses used. so just do not connect nios a[0] that comes from the tristate bridge connect nios a[1] to the lowest adr.bit of your cfi flash device

[Altera_Forum]

Thanks MSchmitt! 

This is a first help for me.   I will make change in my design and make new test!

[Altera_Forum]

another question that is not clear to me 

does your fpga successfully load your fpga image ? just to make shure that it is your fpga systen that is running and not the one already stored on that board. maybe you can check via sysid

[Altera_Forum]

Did you mean FPGA configuration ? Yes, it's the good one. 

 If I program flash with a pof file (obtained from convert programming file in quartus), the good fpga configuration is running but I need to load nios software via jtag after each start up.  But with flash programmer in nios ide, I can't download correctly configuration and software because of this cfi table not found error.

[Altera_Forum]

inside sopc you must set the reset vector to the cfi device as you already mentioned. 

but if your software image is not located at adr offset 0, the first byte of the cfi flash, then you must set the reset address and the offset.  you could have a look into your data memory with the debugger and check what you see inside your memory window. (the nios data master) there you should see correct 16 bit values, if not then there is a mismatch as already said, check your address signals between nios via tristate bridge and the external cfi flash. also check if there are other devices connected to that tristate bridge and if they are unselected as well as all other signals set to a save condition.

[Altera_Forum]

Hi, 

 Thank you very much MSchmitt !!  After changing pin out configuration from nios to flash, I am able to programmate sof + elf files in my flash and all is perfectly loaded at start up!! Great !  :D

[Altera_Forum]

Hi guys, 

I need help with flash programming for a problem very similar to yours!  Like you, I can program flash converting .sof to .pof and load NiosII software via jtag after each start up, or I can program flash with Flash Programmer with .elf and load configuration hardware via jtag. In these cases the system work.  But using Flash Programmer in NiosII IDE, I can't download correctly configuration hardware (.sof), so I can download a complete system (.sof+.elf) working at the power-up.  In the forum I read a lot of discussions over this problem, but all of them solved the problem with a patch of EDS 9.1 SP1, but I'm using Quartus 10.1 and Nios IDE 10.1 that solved this problem.  Someone can help me?

[Altera_Forum]

I'm only using CFI for loading FPGA configuration hardware and nios software. 

 Do I need a EPCS to load FPGA configuration hardware?

[Altera_Forum]

Hi i am doing my finale year project. I also have this problem i can generate my POF then i cant store the nios ii code using flash programmer. Actually i am new to this. I am using DE2-70 board. another question is can i store hardware configuratio pof file and ELf file in a SD Card ? i really expecting some reply thankyou. I am working out this problem in two months thankyou