Help with constraining source synchronous and system synchronous combination

[IMura]

Hello,

I have the following system that is sadly not modifiable anymore : 

The pin names are the same as the 'signal' names. So what we have is an FPGA that is clocked by the REF_CLK, which goes through a PLL but keeps the same frequency as the input. This PLL output clock is the FPGA's system clock and it is also output to the CPLD which in turn uses it to clock in data from the FPGA. The CPLD then pushes the data out to the DAC where the data is clocked by the REF_CLK_2X. 

REF_CLK and REF_CLK_2X both come from the same PLL, 0 phase difference at the PLL and REF_CLK_2X's frequency is twice of the REF_CLK.

I have trouble trying to constrain this design because I can constrain the io_1 in relation to the clk_1 from the FPGA side, making sure that the data transfer between the FPGA and CPLD respects the timing. However, how do I "create the clock" clk_1 going to the CPLD so that it is still related to the REF_CLK and REF_CLK_2X? I can't just use a simple create clock for clk_1 input of the CPLD because that will imply that clk_1 and REF_CLK have 0 phase offset, which is not true and that will make the output to the DAC's constraints false too.

Can anybody help me with this?

Thank you.

[sstrell]

You need the clock output of the PLL (done automatically with newer devices; derive_pll_clocks for older devices or written out as shown below), a generated clock on the clock output port, and a false path so there is only clock analysis and no data analysis on the clock output:

create_generated_clock -name pll_out -source [get_pins <FPGA pll reference clock input pin>] [get_pins <PLL output clock pin for clk_1>] 

create_generated_clock -name clk_1 -source [get_pins <FPGA pll output clock pin for clk_1>] [get_ports clk_1]

set_false_path -to [get_ports clk_1]

[IMura]

Thank you for responding!

I already have those constraints for the FPGA and they work as intended. 

My main issue is with the CPLD constraints : 

In the FPGA project, those create_generated_clock instructions will create the clk_1 output that is related to the ref_clk. How do I then "share/transfer" this information to the CPLD's constraints file? That is, the CPLD's input clk_1's phase offset compared to the ref_clk?

 I tried "faking" this phase offset by using the -waveform argument for the CPLD's clk_1 input but the problem with this is that I don't know for sure what the phase offset is of the clock going out of the FPGA's clk_1 output.

In the FPGA's project, if I use the report_path instruction to get the delay to the clk_1 output, I only get the path delay between the PLL output and the clk_1 port. The PLL is using the "Direct" mode so there will be phase offset between its input reference (REF_CLK) and its output, and due to the routing, the PLL output to the clk_1 port. 

Is it a "better" solution to forward the REF_CLK directly to the clk_1 output, since it's a port to port path, use the delay I get from the report to recreate the clock at the CPLD's clk_1 input?

[sstrell]

You keep mentioning "FPGA" and "CPLD" so I am assuming these are Intel/Altera devices.

For the CPLD, you could use set_clock_latency to specify the delay of the clock arriving at that device, but this is source synchronous so the create_clock coming in should be adjusted using -waveform as you mention, phase shifting from REF_CLK, which should be defined as a virtual clock.

create_clock -name REF_CLK -period <period of REF_CLK>

create_clock -name clk_1 -period <period> -waveform {<rise time> <fall time>} [get_ports <CPLD clk_1 port>]

[Kenny_Tan]

For source synchronous constrain, we have multiple type of constrain like the edge align, center align. You can refer to https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-tq-ea-ss-out.html for example how to constrain it.

[Kenny_Tan]

Not sure if you have further question on this? If no, we shall close this thread.

[Kenny_Tan]

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.