Hi All, I have some doubt regarding FPGA I/O banks.

[NKuma10]

I'm working on FPGA with I/O banks configured as 3.3-V LVCMOS with current strength of 2ma.

I have a requirement to change the current strength to 16ma for some of the signals in this I/O bank which is not supported with 3.3-V LVCMOS. Can i change the I/O bank configuration to 3V LVCMOS? What will be impact on other signals in this I/O bank?

Thanks in advance

[SreekumarR_G_Intel]

Hello Andrew , Thank you giving opportunity to look at issue, Can I assume few things from your input , i) You are not plan to use LVDS in the board using FPGA. Correct ? ii) The VCCIO of bank 5 and 6 connected to the 3.3V. Also Can I assume VREFBx pin is not used for reference voltage ? Correct If my above assumption yes , I don’t think so there is issue to connect the 3.3V bank 5 and bank 6 . In the datasheet can you refer page 7 for the max apply VCCIO ? Note : VCCA must connected to the 2.5V. May I know why you think bank 5 and 6 need to use only for LVDS ? Thank you, Regards, Sree

[SreekumarR_G_Intel]

Hello Naveen , I am sorry , can you please omit above answer that is not with respect to your question . Now about yours . Can I know which device you are plan to use ? it would be good if you provide part number . Thank you , Regards, Sree

[NKuma10]

Hi Sree,

Please find the device and the part number below.

Cyclone IV E : EP4CE55F23C8

And the I/O bank in question is BANK 3.

Thanks

Naveen

[SreekumarR_G_Intel]

Hello Naveen ,

Apologizes for delay ,I think you can use it as long as your voltage compatibility analysis (VIL/VIH and VOL/VOH) satisfy the requirement. Also make sure trough IBIS model you are getting sufficient current strength and check the signal integrity as well.

Thank you ,

Regards,

Sree