I'm designing a Mother Board that includes a PCIe connection to several ARRIA10 devices. The PCIe standard includes a 100 Mhz REF CLK .
I'm using CLK synthesizer (ZL30267 Microsemi) to distribute the PC (root) CLK to all other devices (eight FPGAs). one on board, seven other connected via connectors.
Between the ZL30267 driver and all other FPGAs receivers, i'm biasing the driver output (i'm driving HCSL CLK) and using AC coupling.
For Arria 10 FPGA, we only support DC coupling on HCSL IO standard. Kindly refer to below datasheet page 29
Pls use HCSL with DC coupling only, not AC coupling.