Hierarchy not retained in Modelsim during RTL simulation

[NShan12]

Hello,

I am using QP 20.1.1 STD.

I have a hierarchical design (comprising VHDL and BDF flies), see screenshot (some names hidden):

When I launch RTL Simulation from Quartus, I see that in Modelsim the same project hierarchy do not exist.

"proc_vhd_vec_tst" is my testbench and "i1" is the instance name of my VHDL top module in the testbench file.

As seen in the below screenshot, only ADC1_INST and ADC2_INST can be seen in the modelsim window and not the other instances such as PROC_1 and PROC_2.

Therefore, I am not able to view the internal signals of sub modules in the wave window. How can I retain the hierarchy in modelsim to view the internal signals?

[SyafieqS · Accepted solution]

Naveen,

Seem like the other instance is not in Modelsim is due to unsupported format for Modelsim, you have to convert to HDl in order to simulate it.

https://www.intel.com/content/www/us/en/support/programmable/articles/000078436.html