High Speed Serial IO - Signal Loss Condition Resolution at the Bit Level

[Altera_Forum]

Hello, 

  I have an application where each bit of data I send across the High Speed Serial IO Link (6Gbps) transceiver link is critical and knowing exactly where in my bit sequence (down to the bit level) that a signal loss condition occurred is just as critical. I know the registers for the transceivers are parallel, but if for example I send 16-bits of data across a link to the receiver and an error occurs after the 5th bit is sent will I have access to the 5 good bits at the receiver so that I know exactly where in my bit sequence the error occurred?    Thank you for your help,

[Altera_Forum]

Some errors may be locatable down to the word level by the 88/10B decoder, others may be undetectable. You would need an additional error-detection layer (e. g. by CRC) to detect any error with a specified likelihood and optionally locate an error position.

[Altera_Forum]

For error detection I will be transmitting out a known bit sequence and the receive will know what to expect. I can use that to check for errors. But what I need to be able to do is receive a parital word in the event of an error so that I will know when the error occurred in my bit sequence down the the bit level not just the word level. Is that possible? Can you read a partial word with the receiver?