Community
cancel
Showing results for 
Search instead for 
Did you mean: 
LFrin
Novice
467 Views

How does a PLL behave when switching off the reference clock?

Jump to solution

I have observed a strange behavior of the FPGA PLL (Cyclone V GT), if you take away the reference clock, it still has an low output frequency.

 

Tags (2)
0 Kudos
1 Solution
IDeyn
New Contributor II
68 Views

Hi LFrin!

 

In case of absence of the reference clock, PLL can output a low output frequency.

PLL, in fact, consists of VCO (voltage controlled oscillator) and PFD - phase and frequency detector, which compares two input clocks - reference and looped clock, typically divided version of VCO.

 

The output signal from PFD controls the VCO frequency.

 

So in case of taking away the reference clock, PFD should output constant error signal, which can force VCO frequency to its minimum frequency.

 

// You can see the schematic of PLL for example here - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf - Figure 1.

 

 

 

--

Best regards,

Ivan

View solution in original post

1 Reply
IDeyn
New Contributor II
69 Views

Hi LFrin!

 

In case of absence of the reference clock, PLL can output a low output frequency.

PLL, in fact, consists of VCO (voltage controlled oscillator) and PFD - phase and frequency detector, which compares two input clocks - reference and looped clock, typically divided version of VCO.

 

The output signal from PFD controls the VCO frequency.

 

So in case of taking away the reference clock, PFD should output constant error signal, which can force VCO frequency to its minimum frequency.

 

// You can see the schematic of PLL for example here - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf - Figure 1.

 

 

 

--

Best regards,

Ivan

View solution in original post

Reply