How is an ALM used as Memory cell inside MLAB?

[Sajith_K_Intel]

When an ALM inside MLAB is configured as a 32x2 simple dual-port memory, ALM block at least need 5-bit read address, 5-bit write address, write enable, clock, and byte enable. But for an ALUT, only available ports are 8 inputs (for new architectures).

Does anybody know how it forms all the required ports (write and read addresses,wen,byte enable) for a memory configuration? Are there dedicated ports to ALUT other than its 8 inputs?

I could not find related details in any of the Intel documents. Please suggest if you have some resources.

Thanks in advance.

[sstrell]

I'm not sure of the exact answer to your question, but have you checked out any of the embedded memory user guides? This is the one for Stratix 10:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf

MLABs are made up of 10 ALMs so that's enough inputs for what is required for the whole MLAB. Where are you seeing that an individual ALM can be configured as a fully dual port 32x2 RAM with all those control signals?

#iwork4intel

[Sajith_K_Intel]

This document clearly says "you can configure each ALM in the MLAB as ten 32×2 blocks. The Intel Stratix 10 devices provide one 32×20 simple dual-port SRAM block per MLAB"

The attachment is a view from resource property viewer.

You can see a single ALM placed in MLAB cell, configured as RAM (LUTRAM), and has write address ports, byteenable, write enable, addition to the ALUT inputs used as read address bus. I could not see any documentation detailing about these extra ports. Kindly share if you have some references.

[KhaiChein_Y_Intel]

Hi,

Upon checking, there is only a document about the Intel Stratix 10 LAB and MLAB Structure https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lab.pdf and Embedded Memory block types https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf but not detailing about the extra ports in the RAM.

Thanks.

[Sajith_K_Intel]

Thanks, I read this document already and there are no detailing about LUTRAM ports as you said.

I am not very sure who can answer this question.

[KhaiChein_Y_Intel]

Hi,

I try to create a simple test case similar to the screenshot you have attach here but I could not replicate. Could you provide a simple test case for investigation?

Thanks.

Best regards,

KhaiY

[Sajith_K_Intel]

Now I do not have a testcase, But you should be able to do it by using a ram template, and inferring MLAB memory.

[KhaiChein_Y_Intel]

Hi,

Can you check if the settings are the same?

Thanks

[Sajith_K_Intel]

Your design was not inferring MLABS right? I have attached a sample design here where MLAB is used as memory.

[Sajith_K_Intel]

Do we have any document showing internal architecture of "ALM when used as MLAB cell"?

[KhaiChein_Y_Intel]

Hi,

Unfortunately, there is no document showing the RAM internal architecture.

Thanks.

Best regards,

KhaiY