How many cycles will cost when using a multiplicaiton?

[Altera_Forum]

Just using * as the symbol of multiplication. 

Does it depend on the data bit wide ? Thanks

[Altera_Forum]

Yes. At first cyclone 16*16=32 will cost half of chip and take 16ns. Use megafunction for control it.

[Altera_Forum]

There is no need to use the megafunction unless on special cases. 

 Using a Cyclone III it will multiply up to 18bits*18bits in a single clock cycle. The speed of it depends on the FPGA you use. Most of them can do it up to 300MHz.  What FPGA are you using ?

[Altera_Forum]

--- Quote Start ---  Just using * as the symbol of multiplication.  Does it depend on the data bit wide ? Thanks  --- Quote End ---    The "*" operator will, by itself, produce a purely combinational multiplier. Wi So, the question is not how many cycles it will take but how much delay it will add and, therefore, at which frequency can the design run.  And of course, the answer is that it will depend on the width.

[Altera_Forum]

Thanks you for repling. 

I am using cyclone II ,2c35 I thouht multiplication was implemented in time sequence automatically. So, what's your mean is that it can be done just for one cycle, if the frequence is meet. The reason why I ask how long it will cost is that I found a long delay when outputing result. I just use basic 50 MHz

[Altera_Forum]

No, the VHDL/Verilog operators don't describe sequential behaviour. 

 Yes, it can be done in one cycle if the operating frequency is low enough.   On a Cyclone II, an 18x18 multiplication can run up to 180-260 MHZ, depending on the speed grade.  Larger multiplications will either have to run slower or you'll have to divide them into multiple cycles.

[Altera_Forum]

On a C2S35 you can do up to 35 18x18 single clock cycle multiplications in parallel. 

 See: http://www.altera.com/products/devices/cyclone2/features/multipliers/cy2-multipliers.html  And at 50MHz it works like a charm and has enough slack to meet timing no matter what.  rbugalho I think * sign will infer a proper dedicated multiplier and not a logic based one (if the bit-widths allow it). How sure are you that it will not infer it ?

[Altera_Forum]

Usually, "*" will infer a dedicated multiplier. 

 But this does not conflict with what I said before. Dedicated multiplier blocks can also be configured in a purely combinational mode, without any register stages.  And of course, when you use a "*" operator in a edge sensitive assignment, you get sequential behaviour.

[Altera_Forum]

Oh, my mistake I understood you meant "combinatorial logic fabric". :)