In my design I instantiate a RapidIO core and a ATX PLL core, and the device is Arria10.
clk is the reference clock for RX CDR block in transceiver,
pll_refclk0 is the input clock of ATX PLL,
clk and pll_refclk0 should be driven from the same clock source.
Is clk a differential signal?
Should I connect both of them to the same dedicated reference clock pin?