How should connect an external PLL to a set of transceivers when bonding?

[Altera_Forum]

Hello, 

 edit: apologies for this post, the issue was not with the assignment of the clocks but my instantiation of the megafunction. the correct way to assign the clocks is to assign the fractional-pll output (from the dpa port) to all channels (so long as one of them - channel 1 or 4 - has a central clock divider). this way my design builds and drives the transceivers correctly.  I would like to transmit data, multiplexed across four channels, at an arbitrary rate using GX transceivers on a Stratix V. The transceivers are split across two banks but they are contiguous (Channels 4 & 5 in one bank and 0 & 1 in the next).   I have instantiated the Native PHY megafunction, configured in direct PMA mode using an external PLL. I can drive two transceivers by connecting the DPA outputs* of the PLL to the external clock input of the PHY.   I cannot seem to bond the transceivers however. I reconfigure the PHY to bond using the x6/xN clock network. If I have understood correctly, according to the last entry in Table 2-3 (page 11) of transceiver clocking in stratix v devices (http://www.altera.com/literature/hb/stratix-v/stx5_52003.pdf), I should be able to connect the fPLL output to Channel 4 of the first bank. The device can then use the local x6 network to drive channel 5 and xN to drive channels 0 & 1 on the next bank.    When I do this however Quartus returns an error:     --- Quote Start ---   Error: Clock Divider node '[long hierarchy]|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port. It must be connected to one of the valid ports listed below. File: [long directory]/native_phy/sv_tx_pma_ch.sv Line: 391 Mon 17:52: INFO : Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Mon 17:52: INFO : Info: Can be connected to CLKCDR port of stratixv_channel_pll WYSIWYG ...   --- Quote End ---     If I connect the clock to all the transceivers I receive the error in fitting (which makes sense because I am essentially asking Quartus to route the clock to the transceiver over two routes at the same time):     --- Quote Start ---  Error (175006): Could not find path between the PLL DPA output and destination Transmitter channel Mon 18:29: INFO : Info (175027): Destination: Transmitter channel for I/O [my first transceiver] Mon 18:29: INFO : Info (175015): The I/O pad is constrained to the location PIN_U4 due to: User Location Constraints (PIN_U4) Mon 18:29: INFO : Error (175022): The PLL DPA output could not be placed in any location to satisfy its connectivity requirements Mon 18:29: INFO : Info (175021): The Transmitter channel was placed in location Transmitter channel containing PIN_U4 Mon 18:29: INFO : Info (175029): 11 locations affected Mon 18:29: INFO : Info (175029): PLLDPAOUTPUT_X0_Y21_N0 Mon 18:29: INFO : Info (175029): PLLDPAOUTPUT_X0_Y30_N0 ...   --- Quote End ---     So what is the correct way to do it?     (*I am not sure why but I need to use one of the DPA outputs, not OUTCLK of the generic_pll or Quartus returns the first error)