How should you handle 3.3V I/O pins set to VCCINT on vertical migration between 10CL016 and 10CL025 ?

[MJack11]

We have a design that fits into a 10CL016 but we want to be able to use the 10CL025 in the future if our design requirements change.

I have successfully compiled the design with vertical migration set to 10CL016 and 10CL025 (U256 package)

Several I/O pins on the 10CL016 device are actually GND or VCCINT on the 10CL025 device (for example pad G11 and J12).

The GND pins we have no issue with ... we'll just connect those to ground.

But the VCCINT pins must be connected to 1.2V.

So, for example, the J12 pad on the 10CL016 is a 3v3 LVTTL I/O ... and on the 10CL025 it is a VCCINT pin.

And here's the main question ...

If our board layout has pad J12 connected to VCCINT (1.2V) but we fit the 10CL016 part, the I/O pin will be an input at 1.2V on a 3.3V bank.

This would be right in the middle of the logic level "grey area" so would likely oscillate internally and draw excess current from the 3.3V rail.

What is Intel's recommendation for such pins ?

[YuanLi_S_Intel]

Hi Jackson,

First of all, VCCINT is the power rail pin that provides power to internal logic and VCCIO is the power rail pin that provides power to the IO buffer. Both of them are having different power rail and thus, the scenario in which excess current drawing might not be happening.

Thank You.

[MJack11]

Thank you for replying.

Unfortunately, this doesn't tell me how to connect such pins.

Can you confirm these I/O pins should simply be connected to VCCINT ?

[YuanLi_S_Intel]

Yes, for VCCINT pin, it is connected to either 1.0V or 1.2V supply. Please refer to the pin connection guidelines for cyclone 10 lp

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01021.pdf (Page 9)